Commit Graph

2996 Commits

Author SHA1 Message Date
Joerg Sonnenberger
86802628de Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-12 03:38:30 +00:00
Joerg Sonnenberger
32cf3068d5 Add missing mul aliases for armv4 support. Add checks that armv4 can
assemble the various mul instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-12 03:35:18 +00:00
Saleem Abdulrasool
8009754517 ARM IAS: support emitting constant values in target expressions
A 32-bit immediate value can be formed from a constant expression and loaded
into a register.  Add support to emit this into an object file.  Because this
value is a constant, a relocation must *not* be produced for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199023 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-11 23:03:48 +00:00
Artyom Skrobov
3dbf2472fd Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 16:49:49 +00:00
Artyom Skrobov
6099123db8 Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 16:42:55 +00:00
Saleem Abdulrasool
793e2aaa73 ARM: fix regression caused by r198914
The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 16:22:47 +00:00
Saleem Abdulrasool
7ff05025b0 ARM IAS: support #:{lower,upper}16: for GNU compatibility
The GNU assembler supports prefixing the expression with a '#' to indiciate that
the value that is being moved is infact a constant.  This improves the
compatibility of the integrated assembler's parser for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198916 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 04:38:40 +00:00
Saleem Abdulrasool
003132d48c ARM IAS: support GNU extension for ldrd, strd
The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198915 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 04:38:35 +00:00
Saleem Abdulrasool
4eeee88e91 ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 04:38:31 +00:00
Venkatraman Govindaraju
8ce28c812b [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198909 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 01:48:17 +00:00
Kevin Enderby
d9615670b7 Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions that
branch to the next instruction.  This can not be encoded but can be
turned into a NOP.

rdar://15062072


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 00:43:32 +00:00
Ana Pazos
cb1f0ddce4 [AArch64][NEON] Added UXTL and UXTL2 instruction aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 21:02:13 +00:00
Roman Divacky
edc4b60fca Force emit a relocation for @gnu_indirect_function symbols so that the indirect
resolution works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198780 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 18:50:32 +00:00
David Woodhouse
38b362617c [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198763 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:40 +00:00
David Woodhouse
2634d1f6da [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)
They do *different* things to %esp, so they are not equivalent.

Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198761 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:32 +00:00
David Woodhouse
ab5b9489e9 [x86] Make AsmParser validate registers for memory operands a bit better
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:28 +00:00
David Woodhouse
aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:24 +00:00
David Woodhouse
4f32ce2436 [x86] Use 16-bit addressing where possible in 16-bit mode
Where "where possible" means that it's an immediate value and it's below
0x10000. In fact GAS will either truncate or error with larger values,
and will insist on using the addr32 prefix to get 32-bit addressing. So
perhaps we should do that, in a later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:18 +00:00
David Woodhouse
975fe2cfc3 [x86] Fix JCXZ,JECXZ_32 for 16-bit mode
JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:12 +00:00
David Woodhouse
d7ae82f8f5 [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode
I couldn't see how to do this sanely without splitting RETQ from RETL.

Eric says: "sad about the inability to roundtrip them now, but...".
I have no idea what that means, but perhaps it wants preserving in the
commit comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:07 +00:00
David Woodhouse
1c75f15a60 [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
David Woodhouse
ce8d7befbf [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:49 +00:00
David Woodhouse
1a19e26276 [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:45 +00:00
David Woodhouse
a493812047 [x86] Add OpSize16 to instructions that need it
This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:40 +00:00
Venkatraman Govindaraju
8f5124903f [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 07:47:57 +00:00
Venkatraman Govindaraju
7ceaa8623c [Sparc] Add support for parsing branch instructions and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 06:14:52 +00:00
Saleem Abdulrasool
cb914a32d6 ARM IAS: properly handle expression operands
Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 03:28:14 +00:00
Roman Divacky
7e889af768 In the ELFWriter when writing aliased (.set) symbols dont blindly
take type from the new symbol but merge them so that the type
is never "downgraded".

This is probably quite rare, except for IFUNC symbols which
we used to misassemble, losing the IFUNC type.

Fixes #18372.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 20:17:03 +00:00
David Peixotto
6f9a004738 Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64
This commit adds the pre-UAL aliases of fconsts and fconstd for
vmov.f32 and vmov.f64. They use an InstAlias rather than a
MnemonicAlias to properly support the predicate operand.

We need to support encoded 8-bit constants in order to implement the
pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this
commit also fixes parsing of encoded floating point constants used
in vmov.f32/vmov.f64 instructions. Now we can support assembly code
like this:

  fconsts s0, #0x70

which is equivalent to vmov.f32 s0, #1.0.

Most of the code was already in place to support this feature.
Previously the code was trying to accept encoded 8-bit float
constants for the vmov.f32/vmov.f64 instructions.  It looks like the
support for parsing encoded floats was lost in a refactoring in
commit r148556 and we did not have any tests in place to catch it.

The change in this commit is to keep the parsed value as a 32-bit
float instead of a 64-bit double because that is what the isFPImm()
function expects to find. There is no loss of precision by using a
32-bit float here because we are still limited to an 8-bit encoded
value in the end.

Additionally, we explicitly reject encoded 8-bit floats for
vmovf.32/64. This is the same as the current behavior, but we now do
it explicitly rather than accidently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 18:19:23 +00:00
Venkatraman Govindaraju
dff38618c6 [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc.,
Also, correct the offsets for FixupsKindInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 08:00:49 +00:00
Saleem Abdulrasool
6a4207d263 ARM IAS: allow more depth in contextual diagnostics
Switch the context to be SmallVectors.  This allows for saving additional
context when providing previous emission sites.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198665 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 02:29:00 +00:00
Saleem Abdulrasool
a83f45be97 ARM IAS: refactor unwind context
Move the unwinding context for the ARM IAS into a helper class.  This is purely
a structural refactoring.  A follow up change allows for recording additional
depth to improve diagnostics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 02:28:55 +00:00
Saleem Abdulrasool
8e129852fb ARM IAS: improve .eabi_attribute handling
Parse tag names as well as expressions.  The former is part of the
specification, the latter is for improved compatibility with the GNU assembler.
Fix attribute value handling to be comformant to the specification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 02:28:42 +00:00
Saleem Abdulrasool
307f17b938 MCParser: introduce Note and use it for ARM AsmParser
Introduce a new virtual method Note into the AsmParser.  This completements the
existing Warning and Error methods.  Use the new method to clean up the output
of the unwind routines in the ARM AsmParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 02:28:31 +00:00
Venkatraman Govindaraju
a16f1ce2d9 [Sparc] Add support for parsing memory operands in sparc AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 01:49:11 +00:00
Jack Carter
063564c4c5 [Mips] TargetStreamer Support for .abicalls and .set pic0.
This patch adds .abicalls and .set pic0 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that both the integrated and standalone
assemblers will use for the output for these directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 23:27:31 +00:00
Venkatraman Govindaraju
9429f47d83 [Sparc] Add initial implementation of disassembler for sparc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 08:08:58 +00:00
Craig Topper
30be10a06e Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit mode
The 0x66 prefix toggles between 16-bit and 32-bit addressing mode.
So in 32-bit mode it is used to switch to 16-bit addressing mode for the
following instruction, while in 16-bit mode it's the other way round — it's
used to switch to 32-bit mode instead.

Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode,
and introduce a new OpSize16 bit which is used in 16-bit mode instead.

This is just the basic infrastructure for that change; a subsequent patch
will add the new OpSize16 bit to the 32-bit instructions that need it.

Patch from David Woodhouse.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 06:02:58 +00:00
Craig Topper
93c9401dff [x86] Add basic support for .code16
This is not really expected to work right yet. Mostly because we will
still emit the OpSize (0x66) prefix in all the wrong places, along with
a number of other corner cases. Those will all be fixed in the subsequent
commits.

Patch from David Woodhouse.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 04:55:54 +00:00
Craig Topper
074b501c17 Fix ModR/M byte output for 16-bit addressing modes (PR18220)
Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 19:40:56 +00:00
Venkatraman Govindaraju
db3031fcb8 Add lit.local.cfg for MC/Sparc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198536 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 03:07:04 +00:00
Venkatraman Govindaraju
5d02c84191 [Sparc] Add initial implementation of MC Code emitter for sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198533 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 02:13:48 +00:00
Craig Topper
e43a0f8015 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 01:35:51 +00:00
Ana Pazos
5124fef085 [AArch64][NEON] Added SXTL and SXTL2 instruction aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03 19:20:31 +00:00
Logan Chien
311730494e [arm] Add softvfp to supported FPU names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198313 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 15:50:02 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:29:32 +00:00
Craig Topper
8dff260267 Add two fp test cases I missed in my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 23:15:19 +00:00
Craig Topper
45e6393241 Add more X86 FP stack disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 22:51:53 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 17:21:44 +00:00
Saleem Abdulrasool
4ba4132d62 ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 18:38:01 +00:00