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15758 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
190d0a54c1 Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113009 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:44:26 +00:00
Bruno Cardoso Lopes
2a4460606e Reintroduce a simple function refactoring done in r112934, also without any functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:20:02 +00:00
Bruno Cardoso Lopes
be8b084d8a Reapply piecies of r112942 and r112934 which don't do 
functional changes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:10:35 +00:00
Bruno Cardoso Lopes
b3e0669b8e Reapply Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:55:05 +00:00
Daniel Dunbar
3139422058 Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced 
some infinite loop and select failures.
 - Apologies for eager reverting, but its branch day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:11 +00:00
Daniel Dunbar
78541f258c Revert r112938 "Fix comment", which depends on r112934, which introduced some 
infinite loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:08 +00:00
Daniel Dunbar
a87ccce95b Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh 
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112998 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:05 +00:00
Jim Grosbach
65482b1bb8 Re-apply r112883: 
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 18:37:12 +00:00
Jim Grosbach
fc63300233 Check the local frame alignment for determining whether dynamic stack 
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112986 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 18:28:19 +00:00
Bob Wilson
f572191fe4 Finish converting the rest of the NEON VLD instructions to use pseudo- 
instructions prior to regalloc.  Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 18:16:02 +00:00
Daniel Dunbar
6a8700301c Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6. 
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 15:26:42 +00:00
Benjamin Kramer
df3f25656d Zap dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 12:13:18 +00:00
Bruno Cardoso Lopes
95f1e2d6b5 AVX doesn't support mm operations neither its instrinsics. 
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
4b0c9f3e73 Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:39:08 +00:00
Bob Wilson
eb0c3d3729 Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the 
vabd intrinsic and add and/or zext operations.  In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests.  Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:35:08 +00:00
Bruno Cardoso Lopes
01f0847ce8 Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
5e5342b0a8 - Use specific nodes to match unpckl masks. 
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:24:00 +00:00
Eric Christopher
e5734105da Simple branch instruction support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:47 +00:00
Jakob Stoklund Olesen
3061c4442e Don't call Predicate_* from X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:18 +00:00
Jakob Stoklund Olesen
7853cd0bea Remove Predicate_* calls from MBlaze and XCore 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:16 +00:00
Jakob Stoklund Olesen
7fa846f7d9 Remove Predicate_* calls from Mips 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:13 +00:00
Eric Christopher
56d2b72884 Add basic support for materializing constants (including fp) and 
stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 23:43:26 +00:00
Anton Korobeynikov
ace53f2fbc Properly emit __chkstk call instead of __alloca on non-mingw windows targets. 
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
ed5c711a6e Move insertps mask decoding to header file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:43:39 +00:00
Anton Korobeynikov
c7c62bb3ca Revert win64 changes. They seem to be incomplete 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:31:32 +00:00
Jim Grosbach
1755b3964f For ARM stack frames that utilize variable sized objects and have either 
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:29:01 +00:00
Anton Korobeynikov
2f4fad99ea Properly allocate win64 shadow reg area. 
Patch by Jan Sjodin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
5594560766 Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:51:11 +00:00
Dan Gohman
24bde5bce1 Don't narrow the load and store in a load+twiddle+store sequence unless 
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:18:42 +00:00
Jim Grosbach
5c33f5bf67 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 19:52:39 +00:00
Jim Grosbach
3e234e7579 remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112847 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:44:51 +00:00
Bruno Cardoso Lopes
6b1d0a3b36 Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:40:13 +00:00
Jim Grosbach
bb5a039b76 handle case where a register class is specified 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:18:52 +00:00
Jim Grosbach
e7c1416263 Now that register allocation properly considers reserved regs, simplify the 
ARM register class allocation order functions to take advantage of that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:14:29 +00:00
Jim Grosbach
5a0fabae5a Mask out reserved registers when constructing the set of allocatable regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112828 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 16:31:21 +00:00
Bob Wilson
82a9c8480e Fill in a missing comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 16:17:29 +00:00
Bob Wilson
ffde080ae6 Convert VLD1 and VLD2 instructions to use pseudo-instructions until 
after regalloc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 16:00:54 +00:00
Bruno Cardoso Lopes
3722f007b6 Replace unpckl_undef and unpckh_undef matching with target specific opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
dd69db858c Move condition out to prepare for more matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
ad10fb2b56 Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
d00bfe1f8d become more strict about when it's safe to use X86ISD::MOVLPS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 02:35:51 +00:00
Eric Christopher
1f58741aab Clang's -ccc-host-triple was ignoring the arch specifier on my triple, 
I don't need to implement this quite yet - and not for ConstantInt anyhow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 02:30:46 +00:00
Eric Christopher
1b61ef4b22 This should be TargetMaterializeConstant instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 01:48:11 +00:00
Eric Christopher
eaa204b2f8 One definition of isThumb is plenty, thanks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 01:39:14 +00:00
Jim Grosbach
b0739b7833 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 01:02:06 +00:00
Eric Christopher
318b6eec8d Rework arm fast-isel load and store handling. Move offset computation 
into the "address selection" routine and handle constant materialization
for stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 00:53:56 +00:00
Jim Grosbach
7af3a345a9 trivial cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 00:02:26 +00:00
Jim Grosbach
352f23529c Simplify the tGPR register class now that the register allocators know not 
to try to allocate reserved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 23:50:23 +00:00
Bob Wilson
d0b69cf119 Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, 
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests.  Add auto-upgrade support for the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 23:50:19 +00:00
Bruno Cardoso Lopes
4783a3ee13 Revert r112689, avoid those kind of checks cause they mess up with mmx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:59:03 +00:00