Commit Graph

2770 Commits

Author SHA1 Message Date
Benjamin Kramer
ccc8d3ba06 Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.

Shrinks ARMBaseRegisterInfo.o by ~100k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 13:37:55 +00:00
Benjamin Kramer
36a2138cce Emit the "is an intrinsic overloaded" table as a bitfield.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 02:16:57 +00:00
Benjamin Kramer
b519a0fe0e Emit the intrinsic modref info as a lookup table instead of a huge switch.
Shrinks BasicAliasAnalysis.o from 106k to 56k on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 01:18:32 +00:00
Benjamin Kramer
6c449ebbe6 Implement getSubRegIndex as a linear search on the SubRegTable instead of using a big switch.
- The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts.
- This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 23:46:50 +00:00
Jim Grosbach
9c826d2d3c Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 22:07:56 +00:00
Benjamin Kramer
b9ace0215d Emit the SubRegTable with the smallest possible integer type.
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:57:08 +00:00
Jim Grosbach
eea87153d1 Tidy up. Spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:46:32 +00:00
Jim Grosbach
5d9651df89 Move the subregister indicies enum into the REGINFO_ENUM section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:43:16 +00:00
Jim Grosbach
95b38aea95 Switch TargetRegisterInfo::getSubReg() to use a lookup table.
Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 20:31:17 +00:00
Craig Topper
1f59523521 Convert generated intrinsic attributes to use an array lookup as Chris suggested in PR11951.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 06:32:00 +00:00
Craig Topper
a1c5b8e1e6 Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 02:31:09 +00:00
Craig Topper
930a1ebd92 X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
Craig Topper
9d91c5d31c Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that were added in r151038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 08:42:06 +00:00
Craig Topper
c528e462a1 Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 07:28:11 +00:00
Craig Topper
44d23825d6 Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
Craig Topper
7d9b20792b Reorder some members in MCRegisterClass to remove padding on 64-bit builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 07:36:39 +00:00
Craig Topper
f3e3783012 In generated RegisterInfo files, replace a pointer to the end of an array with just the size of the array to avoid relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 06:54:41 +00:00
Craig Topper
902af25abd Merge some tables in generated RegisterInfo file. Store indices into larger table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 06:23:21 +00:00
Ahmed Charles
b0934ab7d8 Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 11:37:01 +00:00
Craig Topper
28a713b20a Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
Craig Topper
9e3d0b3351 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
Benjamin Kramer
88b6fc06db Make the EDis tables const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 14:51:07 +00:00
Benjamin Kramer
953362cdfb Reuse the enum names from X86Desc in the X86Disassembler.
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 14:50:54 +00:00
Benjamin Kramer
c667ba69ac Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10 13:18:44 +00:00
Benjamin Kramer
2c6ae095b8 Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 12:35:37 +00:00
Benjamin Kramer
133f9d9894 Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64.
No change on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 11:25:09 +00:00
James Molloy
3015dfb7d7 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
Craig Topper
f41ab77847 More tweaks to get the size of the X86 disassembler tables down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 08:58:07 +00:00
Craig Topper
ce8f4c58d8 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 07:45:30 +00:00
Benjamin Kramer
9bcc7a6973 Don't map registers to the invalid dwarf register (-1). It's the default value.
X86GenRegisterInfo.inc | 1032 -------------------------------------------------
  1 file changed, 1032 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 18:46:26 +00:00
Benjamin Kramer
90a468c424 Value initialize MCRegisterClasses. Not sure how could miss this during the MCTargetDesc refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 14:43:53 +00:00
Craig Topper
655b8de7b2 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
Brendon Cahoon
ffbd0715fa Increment DFAStateEntryTable index for sentinel entry.
When adding the {-1, -1} entry to the DFAStateInputTable, we
need to increment the index used to populate the DFAStateEntryTable.
Otherwise, the entry table will be off by one for each transition
after the {-1, -1} entry. PR11908.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:08:25 +00:00
Jakob Stoklund Olesen
b5af2d943e Specify SubRegIndex components on the index itself.
It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:16:41 +00:00
Jakob Stoklund Olesen
ee599209e6 Fix a bug in the TopoOrderRC comparison function.
The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.

This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149549 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 22:19:26 +00:00
Jakob Stoklund Olesen
f18a9a2314 Avoid emitting empty arrays, they're not standard C++.
It's only by luck that we haven't produced any yet, and clang refuses to
compile them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149546 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 22:12:51 +00:00
Jakob Stoklund Olesen
ed2d17b2d4 Don't assign a value to NUM_TARGET_NAMED_SUBREGS.
It was wrong and completely unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 21:51:53 +00:00
Jakob Stoklund Olesen
90498b195b Move the composite map into CodeGenSubRegIndex.
Each SubRegIndex keeps track of how it composes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 21:44:11 +00:00
Jakob Stoklund Olesen
5fcc156344 Add a TableGen CodeGenSubRegIndex class.
This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 20:57:55 +00:00
Jim Grosbach
f35307ceac Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148856 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:06:59 +00:00
Owen Anderson
4f8dc7b17a Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:29 +00:00
Jakob Stoklund Olesen
5b52f6d655 Add an (interleave A, B, ...) SetTheory operator.
This will interleave the elements from two or more lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:06:05 +00:00
Jakob Stoklund Olesen
31867660cb Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
ec572539dd Add TableGen support for callee saved registers.
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:46:58 +00:00
Devang Patel
40bced0306 Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:30:45 +00:00
David Blaikie
58bd1510a4 Provide better messages in llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 07:00:13 +00:00
David Blaikie
fdebc38523 Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 04:43:56 +00:00
David Blaikie
2dd674fdce Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 23:24:27 +00:00
Jakob Stoklund Olesen
794481d5ca Skip the NAME field when forming tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 22:23:50 +00:00
Jakob Stoklund Olesen
8dd6f0c835 Delete CodeInit and CodeRecTy from TableGen.
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 03:38:34 +00:00