Nate Begeman
ed42853be1
All PPC instructions are now auto-printed
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32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-04 05:00:00 +00:00
Nate Begeman
b7a8f2cdaa
Convert remaining X-Form and Pseudo instructions over to asm writer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-02 08:13:00 +00:00
Nate Begeman
cc8bd9ca7c
convert M and MD form instructions to generated asm writer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-31 02:28:08 +00:00
Nate Begeman
07aada8b0f
Move yet more instructions over to being printed by the generated asm writer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-30 02:28:06 +00:00
Nate Begeman
6b3dc55ef8
Convert A-Form instructions to auto-generated asm writer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-29 22:45:13 +00:00
Nate Begeman
d332fd54f5
Improvements to int->float cast code for PPC-64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16105 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-29 22:02:43 +00:00
Nate Begeman
f2f0781a10
Implement the following missing functionality in the PPC backend:
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cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16081 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-29 08:19:32 +00:00
Nate Begeman
c3306120cc
Move XForm instructions over to the auto-generated asm writer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-21 05:56:39 +00:00
Nate Begeman
b47321ba2b
Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-20 09:56:22 +00:00
Nate Begeman
81d265d692
Clean up floating point instruction selection.
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Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15913 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-19 05:20:54 +00:00
Chris Lattner
0ea3171fbf
Convert all of the DForm_6* operations, which makes all of the Zimm16 users
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dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-15 05:46:14 +00:00
Chris Lattner
97b2a2e389
Convert the DForm_4 over to the asmprintergen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-15 05:20:16 +00:00
Chris Lattner
7bb424fafc
Print mflr using the asmwriter generator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15749 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-14 23:27:29 +00:00
Nate Begeman
b0b8b93e58
Add indexed forms of load doubleword and load word algebraic for 64 bit targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15743 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-14 22:12:20 +00:00
Nate Begeman
244e64ead2
Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-13 02:19:26 +00:00
Misha Brukman
55eee3dc7a
Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15668 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 23:33:34 +00:00
Misha Brukman
f1f6cef161
Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15667 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 20:56:14 +00:00
Misha Brukman
96b6110685
Add doubleword load/store (64-bit only).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15665 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 15:54:36 +00:00
Nate Begeman
b64af918cb
Fix casts of float to unsigned long
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Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-10 20:42:36 +00:00
Misha Brukman
4ad7d1bee7
Use instruction formats as defined in the PowerPC ISA manual
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15577 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-09 17:24:04 +00:00
Misha Brukman
68f3459994
Remove unused opcodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15447 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-03 20:23:44 +00:00
Misha Brukman
37dcae63eb
* Use simpler instruction templates to define instructions
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* Fix several extended opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15423 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-02 21:58:52 +00:00
Misha Brukman
28791dd17f
Separate instruction formats from instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15414 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-02 16:54:54 +00:00
Misha Brukman
8c02c1cbb8
Renamed files:
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* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 23:29:16 +00:00
Misha Brukman
f228fa0580
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 18:35:54 +00:00
Misha Brukman
53f567817c
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15272 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 17:15:05 +00:00
Misha Brukman
53d9a48855
Add SUBI instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15077 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-21 15:53:04 +00:00
Misha Brukman
86ddcf9d4f
Differentiate between global and weak symbol loads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15037 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-20 15:52:25 +00:00
Misha Brukman
2bf5438931
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14895 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-16 20:33:41 +00:00
Misha Brukman
c661c3001c
* Coalesce the handy CALL* alias opcodes with the standard ones
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* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14511 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-30 22:00:45 +00:00
Misha Brukman
5fa2b028b8
* Use LA instead of LWZ for LoadLoAddr
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* Specify the isCall bit and caller-save registers for some call instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14501 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-29 23:37:36 +00:00
Misha Brukman
3905b57442
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14470 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-28 18:27:08 +00:00
Misha Brukman
b2edb443e0
Set isBranch and isTerminator bits on all branch instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14469 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-28 18:23:35 +00:00
Misha Brukman
5dfe3a9c3b
Initial revision
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-21 16:55:25 +00:00