Commit Graph

53825 Commits

Author SHA1 Message Date
Jim Grosbach
22378fd664 ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 07:23:53 +00:00
Argyrios Kyrtzidis
541b2a4aa3 In MemoryBuffer::getOpenFile() make sure that the buffer is null-terminated if
the caller requested a null-terminated one.

When mapping the file there could be a racing issue that resulted in the file being larger
than the FileSize passed by the caller. We already have an assertion
for this in MemoryBuffer::init() but have a runtime guarantee that
the buffer will be null-terminated, so do a copy that adds a null-terminator.

Protects against crash of rdar://11161822.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 04:23:56 +00:00
Jim Grosbach
b657a90929 ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.

rdar://11153753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 03:17:53 +00:00
Jakob Stoklund Olesen
9243c4f7c5 Pass the right sign to TLI->isLegalICmpImmediate.
LSR can fold three addressing modes into its ICmpZero node:

  ICmpZero BaseReg + Offset      => ICmp BaseReg, -Offset
  ICmpZero -1*ScaleReg + Offset  => ICmp ScaleReg, Offset
  ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg

The first two cases are only used if TLI->isLegalICmpImmediate() likes
the offset.

Make sure the right Offset sign is passed to this method in the second
case. The ARM version is not symmetric.

<rdar://problem/11184260>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 03:10:56 +00:00
Akira Hatanaka
56ce6b3520 Reapply 154038 without the failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 22:16:36 +00:00
Owen Anderson
657a4e774c Revert r154038. It was causing make check failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 21:18:58 +00:00
Pete Cooper
ef74ca6a41 REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub register indices on the source registers. No simple test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 21:03:25 +00:00
Benjamin Kramer
e25a2bd2e3 Fix a C++11 UDL conflict.
Still not fixed in the standard ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 20:33:56 +00:00
Pete Cooper
9751b81fc9 f16 FREM can now be legalized by promoting to f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 19:36:31 +00:00
Akira Hatanaka
e825fb3888 Fix LowerGlobalAddress to produce instructions with the correct relocation
types for N32 ABI. Add new test case and update existing ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 19:02:38 +00:00
Akira Hatanaka
c75ceb7809 Fix LowerJumpTable to produce instructions with the correct relocation
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:31:32 +00:00
Akira Hatanaka
86a2733055 Fix LowerConstantPool to produce instructions with the correct relocation
types for N32 ABI and update test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:26:12 +00:00
Jakob Stoklund Olesen
c5041cac7d Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.

<rdar://problem/11182914>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:23:42 +00:00
Jakob Stoklund Olesen
1487cb3a5a Remove spurious debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:23:38 +00:00
Akira Hatanaka
03d830e4f9 Fix LowerBlockAddress to produce instructions with the correct relocation
types for N32 ABI and update test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:22:53 +00:00
Rafael Espindola
26c8dcc692 Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 12:51:34 +00:00
Hongbin Zheng
00b73a5e44 LoopUnrollPass: Use variable "Threshold" instead of "CurrentThreshold" when
reducing unroll count, otherwise the reduced unroll count is not taking
  the "OptimizeForSize" attribute into account.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154007 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 11:44:08 +00:00
Benjamin Kramer
a95b4ebf3c Move yaml::Stream's dtor out of line so it can see Scanner's dtor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 08:53:34 +00:00
Craig Topper
8d41a1a7e6 Remove default case from switch that was already covering all cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 04:42:42 +00:00
Pete Cooper
e5ae51a38f Removed useless switch for default case when switch was covering all the enum values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 00:53:04 +00:00
Michael J. Spencer
c35146b725 Sorry about that. MSVC seems to accept just about any random string you give it ;/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 23:36:44 +00:00
Michael J. Spencer
93210e847a Add YAML parser to Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153977 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 23:09:22 +00:00
Pete Cooper
2ce63c7352 Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 22:57:55 +00:00
Pete Cooper
dda3a099a0 Removed one last bad continue statement meant to be removed in r153914.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 22:18:49 +00:00
Chad Rosier
9dbb018b36 Fix an issue in SimplifySetCC() specific to vector comparisons.
When folding X == X we need to check getBooleanContents() to determine if the
result is a vector of ones or a vector of negative ones. 

I tried creating a test case, but the problem seems to only be exposed on a
much older version of clang (around r144500).
rdar://10923049


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 20:11:24 +00:00
Eric Christopher
fa5b050136 Fix thinko check for number of operands to be the one that actually
might have more than 19 operands. Add a testcase to make sure I
never screw that up again.

Part of rdar://11026482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 17:55:42 +00:00
Dylan Noblesmith
75e3b7fb8f ARMDisassembler: drop bogus dependency on ARMCodeGen
And indirectly, a dependency on most of the core LLVM optimization
libraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 15:48:14 +00:00
Dylan Noblesmith
70debecde6 Object: drop bogus VMCore dependency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 15:48:10 +00:00
Bill Wendling
5fdf475697 The speedup doesn't appear to have been from this, but was an anomaly of my testing machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 11:19:21 +00:00
Bill Wendling
f563fc35c8 Reserve space for the eventual filling of the vector. This gives a small speedup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153949 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 10:50:09 +00:00
Anton Korobeynikov
9cd5e7a478 Make PPCCompilationCallbackC function to be static, so there will be no need to issue call via
PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 06:59:28 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 05:20:24 +00:00
Akira Hatanaka
9dd16d41a2 Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 03:01:13 +00:00
Akira Hatanaka
02365945a6 Revert r153924. There were buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 02:51:09 +00:00
Akira Hatanaka
885020a7a7 MIPS disassembler support.
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 02:20:58 +00:00
Eric Christopher
6126a1e189 Add a line number for the scope of the function (starting at the first
brace) so that we get more accurate line number information about the
declaration of a given function and the line where the function
first starts.

Part of rdar://11026482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 00:43:49 +00:00
Pete Cooper
2e267ae7b8 Fixes to r153903. Added missing explanation of behaviour when the VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 00:28:46 +00:00
Pete Cooper
789d5d85ba Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 22:44:18 +00:00
Jakob Stoklund Olesen
e3b23cde80 Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.

Patch by Shamil Kurmangaleev!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 22:30:39 +00:00
Pete Cooper
8a06af9669 Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 22:22:53 +00:00
Bill Wendling
3197b4453d Add an option to turn off the expensive GVN load PRE part of GVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 22:16:50 +00:00
Owen Anderson
29f60f359b Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 22:10:29 +00:00
Lang Hames
be9fe49b17 During two-address lowering, rescheduling an instruction does not untie
operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 19:58:43 +00:00
Akira Hatanaka
a551a48402 Initial 64 bit direct object support.
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.

The test case checks for both big and little endian flavors.

Patch by Jack Carter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 19:25:22 +00:00
Hal Finkel
70272aac56 The binutils for the IBM BG/P are too old to support CFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 19:09:04 +00:00
Hal Finkel
a47406c442 Add triple support for the IBM BG/P and BG/Q supercomputers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 18:31:33 +00:00
Eric Christopher
60777d8eaf Turn on the accelerator tables for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 17:58:52 +00:00
Stepan Dyatkovskiy
aad9c3f17a Fast fix for PR12343:
http://llvm.org/bugs/show_bug.cgi?id=12343

We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling.

Fix forbids this case for unswitching.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 17:16:45 +00:00
Roman Divacky
466958c2a0 Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 15:49:30 +00:00
Benjamin Kramer
c97ef618d2 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 08:32:38 +00:00