Commit Graph

78798 Commits

Author SHA1 Message Date
Lang Hames
78906c6555 [RuntimeDyld] Always allocate at least 1 byte for object sections in the JIT to
ensure that section addresses are distinct.

mapSectionAddress will fail if two sections are allocated the same address,
which can happen if any section has zero size (since malloc(0) is implementation
defined). Unfortunately I've been unable to repro this with a simple test case.

Fixes <rdar://problem/20314015>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234299 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 06:27:56 +00:00
Lang Hames
d27a0a9b2c [Orc] Save all the x86-64 GPRs before re-entering the JIT.
The re-entry code should work for all calling conventions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234298 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 06:12:21 +00:00
Duncan P. N. Exon Smith
c513d37e67 Try a third time to fix MSVC build after r234290
I have no idea what MSVC means with its error text here :(.

http://lab.llvm.org:8011/builders/sanitizer-windows/builds/2310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234295 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 05:03:47 +00:00
Duncan P. N. Exon Smith
faa23b7768 Try again to fix MSVC build after r234290
Still failing:

http://lab.llvm.org:8011/builders/sanitizer-windows/builds/2309

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234294 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 04:49:13 +00:00
Duncan P. N. Exon Smith
ea6394ec99 Try to fix MSVC build after r234290
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/2308

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234292 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 04:33:42 +00:00
Duncan P. N. Exon Smith
92d1a52362 DebugInfo: Remove DITypedArray<>, replace with typedefs
Replace all uses of `DITypedArray<>` with `MDTupleTypedArrayWrapper<>`
and `MDTypeRefArray`.  The APIs are completely different, but the
provided functionality is the same: treat an `MDTuple` as if it's an
array of a particular element type.

To simplify this patch a bit, I've temporarily typedef'ed
`DebugNodeArray` to `DIArray` and `MDTypeRefArray` to `DITypeArray`.
I've also temporarily conditionalized the accessors to check for null --
eventually these should be changed to asserts and the callers should
check for null themselves.

There's a tiny accompanying patch to clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234290 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 04:14:33 +00:00
Duncan P. N. Exon Smith
b135631d2e DebugInfo: Remove DICompositeType mutation API
Change `DIBuilder` to mutate `MDCompositeTypeBase` directly, and remove
the wrapping API in `DICompositeType`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234289 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 04:12:02 +00:00
Duncan P. N. Exon Smith
351071c069 DebugInfo: Use DebugNodeRef in MDImportedEntity::getEntity()
A quick cleanup to sue `DebugNodeRef` instead of `Metadata*` for
`MDImportedEntity::getEntity()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234288 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 04:07:31 +00:00
Duncan P. N. Exon Smith
c6ac80b701 DebugInfo: Move DIExpression bit-piece API to MDExpression
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234286 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 03:49:59 +00:00
Duncan P. N. Exon Smith
fb2e97e4aa DebugInfo: Remove special iterators from DIExpression
Remove special iterators from `DIExpression` in favour of same in
`MDExpression`.  There should be no functionality change here.

Note that the APIs are slightly different: `getArg(unsigned)` counts
from 0, not 1, in the `MDExpression` version of the iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234285 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 03:45:57 +00:00
Adam Nemet
ad8a6b66d9 [LoopAccesses] New API to query if memchecks are necessary after partitioning
This is used by Loop Distribution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234283 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 03:35:26 +00:00
Duncan P. N. Exon Smith
5f3bcf7dc4 DebugInfo: Move DIFlag-related API from DIDescriptor to DebugNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234274 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 01:21:40 +00:00
Duncan P. N. Exon Smith
329f8219cd IR: Rename MDSubrange::getLo() to getLowerBound()
During initial review, the `lo:` field was renamed to `lowerBound:`.
Make the same change to the C++ API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234267 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-07 00:39:59 +00:00
Duncan P. N. Exon Smith
4a4ba5c687 IR: Fix -Werror noasserts build after r234255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234259 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 23:34:41 +00:00
Duncan P. N. Exon Smith
0477045c32 CodeGen: Stop using DIDescriptor::is*() and auto-casting
Same as r234255, but for lib/CodeGen and lib/Target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234258 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 23:27:40 +00:00
Duncan P. N. Exon Smith
573ca050d2 Transforms: Stop using DIDescriptor::is*() and auto-casting
Same as r234255, but for lib/Analysis and lib/Transforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234257 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 23:27:00 +00:00
Duncan P. N. Exon Smith
1545953510 IR: Stop using DIDescriptor::is*() and auto-casting
`DIDescriptor`'s subclasses allow construction from incompatible
pointers, and `DIDescriptor` defines a series of `isa<>`-like functions
(e.g., `isCompileUnit()` instead of `isa<MDCompileUnit>()`) that clients
tend to use like this:

    if (DICompileUnit(N).isCompileUnit())
      foo(DICompileUnit(N));

These construction patterns work together to make `DIDescriptor` behave
differently from normal pointers.

Instead, use built-in `isa<>`, `dyn_cast<>`, etc., and only build
`DIDescriptor`s from pointers that are valid for their type.

I've split this into a few commits for different parts of LLVM and clang
(to decrease the patch size and increase the chance of review).
Generally the changes I made were NFC, but in a few places I made things
stricter if it made sense from the surrounded code.

Eventually a follow-up commit will remove the API for the "old" way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234255 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 23:18:49 +00:00
Rafael Espindola
7bdc1cb690 Use sext in fast isel.
Fast isel used to zero extends immediates to 64 bits. This normally goes
unnoticed because the value is truncated to 32 bits for output.

Two cases were it is noticed:

* We fail to use smaller encodings.
* If the original constant was smaller than i32.

In the tests using i1 constants, codegen would change to use -1, which is fine
(and matches what regular isel does) since only the lowest bit is then used.

Instead, this patch then changes the ir to use i8 constants, which looks more
like what clang produces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234249 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 22:29:07 +00:00
Duncan P. N. Exon Smith
a10307bf95 DebugInfo: Reimplement DIRef<>::resolve() using TypedDebugNodeRef<>
Gut `DIRef<>::resolve()`, reimplementing it using
`TypedDebugNodeRef<>::resolve()`.  Use three separate functions rather
than some sort of type traits, since the latter (i.e., mapping `DIScope`
=> `MDScope`) seems heavy-handed.  I don't expect `DIRef<>` to last much
longer in tree anyway.

As a drive-by fix, make `TypedDebugNodeRef<>::resolve()` do the right
thing with `nullptr`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234248 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 22:27:37 +00:00
Duncan P. N. Exon Smith
cf0d94f462 DebugInfo: Drop confusing forwarding API from DILexicalBlockFile
Remove `DILexicalBlockFile::getScope()` (whose last use was removed from
clang in r234245), which illegally returned a `DILexicalBlock` despite
its scope sometimes being an `MDSubprogram`.  Also remove the
`getLineNumber()` and `getColumnNumber()` methods that just forwarded to
`DILexicalBlock`'s versions, since there don't seem to be any callers.

Note that the block of code removed from `DebugInfo.cpp` was actually
dead code, since `isLexicalBlock()` (the previous branch) always returns
true when `isLexicalBlockFile()` returns true.

An earlier (broken and untested) version of this was squashed into
r234222 and reverted in r234225.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234246 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 22:07:46 +00:00
David Blaikie
4f67d9167d ArgPromo: Bail out earlier for varargs functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234224 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 21:27:31 +00:00
Ismail Pazarbasi
aa5880df12 Move checkInterfaceFunction to ModuleUtils
Summary:
Instead of making a local copy of `checkInterfaceFunction` for each
sanitizer, move the function in a common place.

Reviewers: kcc, samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8775

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 21:09:08 +00:00
David Blaikie
af1023588e [opaque pointer type] Avoid using PointerType::getElementType when parsing IR
A few calls are left in for error checking - but I'm commenting those
out & trying to build some IR tests (aiming for Argument Promotion to
start with). When I get any of these tests passing I may add flag to
disable the checking so I can add tests that pass with the assertion in
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 20:59:48 +00:00
Duncan P. N. Exon Smith
1ea24954c6 DebugInfo: Remove DIDescriptor::Verify()
Remove `DIDescriptor::Verify()` and the `Verify()`s from subclasses.
They had already been gutted, and just did an `isa<>` check.

In a couple of cases I've temporarily dropped the check entirely, but
subsequent commits are going to disallow conversions to the
`DIDescriptor`s directly from `MDNode`, so the checks will come back in
another form soon enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 19:49:39 +00:00
Duncan P. N. Exon Smith
e009b6fd92 DebugInfo: Use MDTypeRef throughout the hierarchy
Use `MDTypeRef` (etc.) in the new debug info hierarchy rather than raw
`Metadata *` pointers.

I rolled in a change to `DIBuilder` that looks unrelated: take `DIType`
instead of `DITypeRef` as type arguments when creating variables.
However, this was the simplest way to use `MDTypeRef` within the
functions, and didn't require any cleanups from callers in clang (since
they were all passing in `DIType`s anyway, relying on their implicit
conversions to `DITypeRef`).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234197 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 19:03:45 +00:00
Reid Kleckner
ebb3c53316 [WinEH] Don't sink allocas into child handlers
The uselist isn't enough to infer anything about the lifetime of such
allocas. If we want to re-add this optimization, we will need to
leverage lifetime markers to do it.

Fixes PR23122.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234196 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 18:50:38 +00:00
Tim Northover
8af3f965e0 ARM: do not relax Thumb1 -> Thumb2 if only Thumb1 is available.
After recognising that a certain narrow instruction might need a relocation to
be represented, we used to unconditionally relax it to a Thumb2 instruction to
permit this. Unfortunately, some CPUs (e.g. v6m) don't even have most Thumb2
instructions, so we end up emitting a completely invalid instruction.

Theoretically, ELF does have relocations for these situations; but they are
fairly unusable with such short ranges and the ABI document even says they're
documented "for completeness". So an error is probably better there too.

rdar://20391953

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234195 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 18:44:42 +00:00
Simon Pilgrim
2ec7242600 [X86][SSE] Use (V)PINSRB for direct byte insertion in 16i8 buildvector on SSE4.1 targets
This patch allows SSE4.1 targets to use (V)PINSRB to create 16i8 vectors by inserting i8 scalars directly into a XMM register instead of merging pairs of i8 scalars into a i16 and using the SSE2 PINSRW instruction.

This allows folding of byte loads and reduces scalar register usage as well.

Differential Revision: http://reviews.llvm.org/D8839

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 18:39:00 +00:00
Duncan P. N. Exon Smith
05652b6afa DebugInfo: Create MDTypeRef, etc., to replace DITypeRef
Create a string-based wrapper in the debug info hierarchy for type
references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 18:02:43 +00:00
Duncan P. N. Exon Smith
8eb45116ef Metadata: Add typed array-like wrapper for MDTuple
Add `MDTupleTypedArrayWrapper`, a wrapper around `MDTuple` that adapts
it to look like an array and cast its operands to the given type.  This
is designed to be a replacement for `DITypedArray<>`, which is in the
`DIDescriptor` hierarchy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234183 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:45:07 +00:00
Duncan P. N. Exon Smith
c6370a13cf DebugInfo: Remove dead code for accessing fields
Most fields are now accessed via the new debug info hierarchy.  I'll
make the rest of this code dead soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234182 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:21:05 +00:00
Duncan P. N. Exon Smith
e75a8c3855 AutoUpgrade: Remove obsolete dbg.declare/value upgrade
This upgrade of `@llvm.dbg.declare` and `@llvm.dbg.value` isn't useful,
since it's for an old debug info version.  The calls will get stripped
anyway by `UpgradeDebugInfo()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234181 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:17:47 +00:00
Jingyue Wu
10483b93ea [SLSR] consider &B[S << i] as &B[(1 << i) * S]
Summary: This reduces handling &B[(1 << i) * s] to handling &B[i * S].

Test Plan: slsr-gep.ll

Reviewers: meheff

Subscribers: sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D8837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234180 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:15:48 +00:00
Simon Pilgrim
7d424d47d3 [DAGCombiner] Add support for FCEIL, FFLOOR and FTRUNC vector constant folding
Differential Revision: http://reviews.llvm.org/D8715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234179 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:15:41 +00:00
Duncan P. N. Exon Smith
fe42afc0e5 Verifier: Check composite type template params
Add missing checks for `templateParams:` in `MDCompositeType`.  Pull the
current check for `MDSubprogram` to reduce duplicated code and fix it up
to print a good message when the immediate operand isn't an `MDTuple`
(as a drive-by, make the same fix to `variables:` in `MDSubprogram`).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:04:58 +00:00
Duncan P. N. Exon Smith
b508daa9c2 DebugInfo: Use MDFile instead of accessing operands directly, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234175 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 16:43:40 +00:00
Rafael Espindola
6ba6e554c7 Use a comma after the unique keyword.
H.J. Lu noted that all .section options are separated by a comma.

This patch changes the syntax of unique to require one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 16:34:41 +00:00
Sanjay Patel
28827bea16 fix typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234171 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 16:21:12 +00:00
Rafael Espindola
e17e7a2400 Remove unnecessary uses of AliasedSymbol.
As pr19627 points out, every use of AliasedSymbol is likely a bug.

The main use was to avoid the oddity of a variable showing up as undefined. That
was fixed in r233995, which made these calls nops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234169 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 16:10:05 +00:00
Aaron Ballman
1f1fecb823 Removing a spurious space; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234168 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 16:09:13 +00:00
Rafael Espindola
9428f184be Be consistent when deciding if a relocation is needed.
Before when deciding if we needed a relocation in A-B, we wore only checking
if A was weak.

This fixes the asymmetry.

The "InSet" argument should probably be renamed to "ForValue", since InSet is
very MachO specific, but doing so in this patch would make it hard to read.

This fixes PR22815.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 15:27:57 +00:00
Pawel Bylica
0aa299a454 Test commit. Improve comments in APInt. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234158 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 13:31:39 +00:00
Rafael Espindola
83be4429b2 Store the sh_link of ARM_EXIDX directly in MCSectionELF.
This avoids some pretty horrible and broken name based section handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234142 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 04:25:18 +00:00
Rafael Espindola
6254dcc14b Simplify this function a bit. NFC.
The case values are not a tidy enum we can fully cover. They even ovelap
over the various extension.

Just use a default:

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234140 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 03:16:51 +00:00
Rafael Espindola
01183f6492 Simplify mapping from relocation sections to relocated sections.
Just store the section in MCSectionELF. This avoids multiple hash lookups.

This will also be used by ARM_EXIDX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234139 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 03:09:30 +00:00
Lang Hames
d0440d2705 [Orc] Tidy up the assembly for the x86-64 resolver block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234138 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 03:01:29 +00:00
David Blaikie
5d3a7abed9 clang-format my last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234127 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-05 22:44:57 +00:00
David Blaikie
7b0e5b8edc [opaque pointer type] The last of the GEP IRBuilder API migrations
There's still lots of callers passing nullptr, of course - some because
they'll never be migrated (InstCombines for bitcasts - well they don't
make any sense when the pointer type is opaque anyway, for example) and
others that will need more engineering to pass Types around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234126 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-05 22:41:44 +00:00
Simon Pilgrim
4cd2e19856 [DAGCombiner] Merge FMUL Scalar and Vector constant canonicalization to RHS. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234118 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-05 14:30:37 +00:00
David Blaikie
0a63904a98 [opaque pointer type] More GEP API migrations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234108 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 21:07:10 +00:00
Sanjay Patel
61e62937c1 less space; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234106 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 21:05:52 +00:00
Rafael Espindola
d15c1cfeb1 Don't mix overload and default values.
It makes it hard to see which one is being called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234100 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 18:16:01 +00:00
Rafael Espindola
903f4a2051 Implement unique sections with an unique ID.
This allows the compiler/assembly programmer to switch back to a
section. This in turn fixes the bootstrap failure on powerpc (tested
on gcc110) without changing the ppc codegen at all.

I will try to cleanup the various getELFSection overloads in a  followup patch.
Just using a default argument now would lead to ambiguities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234099 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 18:02:01 +00:00
Simon Pilgrim
b8d7733666 [DAGCombiner] Canonicalize vector constants for ADD/MUL/AND/OR/XOR re-association
Scalar integers are commuted to move constants to the RHS for re-association - this ensures vectors do the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234092 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 10:20:31 +00:00
Craig Topper
4d1e15c54f [X86] Apply AddedComplexity consistently for similar patterns. This keeps them together in the DAGISel tables and reduces table size slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234086 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 04:22:12 +00:00
Craig Topper
4ed0907298 [X86] Add a comment about the change in r234075.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234079 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 02:31:43 +00:00
Craig Topper
b1ff87ec86 [X86] Don't use GR64 register 'and with immediate' instructions if the immediate is zero in the upper 33-bits or upper 57-bits. Use GR32 instructions instead.
Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero.

Fixes PR23100.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234075 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-04 02:08:20 +00:00
David Majnemer
45221a75fb [WinEH] Fill out CatchHigh in the TryBlockMap
Now all fields in the WinEH xdata have been filled out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234067 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 23:37:34 +00:00
David Blaikie
f259550935 [opaque pointer type] More GEP IRBuilder API migrations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234064 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 23:03:54 +00:00
David Majnemer
8431785c5e [WinEH] Fill out .xdata for catch objects
This add support for catching an exception such that an exception object
available to the catch handler will be initialized by the runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234062 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 22:49:05 +00:00
David Majnemer
f89ce9a09d [WinEH] Sink UnwindHelp completely out of IR
We don't need to represent UnwindHelp in IR.  Instead, we can use the
knowledge that we are emitting the parent function to decide if we
should create the UnwindHelp stack object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234061 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 22:32:26 +00:00
Andrew Kaylor
2902e1ca86 Fixing a memory leak in WinEHPrepare
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234059 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 21:44:17 +00:00
David Blaikie
4a86b381a3 [opaque pointer type] More GEP IRBuilder API migrations...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 21:33:42 +00:00
David Blaikie
4615ac61c5 Use early returns to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234057 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 21:32:06 +00:00
David Majnemer
701c2fca7e [InstCombine] Use DataLayout to determine vector element width
InstCombine didn't realize that it needs to use DataLayout to determine
how wide pointers are.  This lead to assertion failures.

This fixes PR23113.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 20:18:40 +00:00
Andrew Kaylor
bd2c26b992 Fixing a build error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234045 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 19:55:30 +00:00
Andrew Kaylor
3c430466e9 Fixing build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234043 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 19:45:32 +00:00
David Blaikie
cf57d81b6e [opaque pointer type] More GEP API migrations in IRBuilder uses
The plan here is to push the API changes out from the common components
(like Constant::getGetElementPtr and IRBuilder::CreateGEP related
functions) and just update callers to either pass the type if it's
obvious, or pass null.

Do this with LoadInst as well and anything else that comes up, then to
start porting specific uses to not pass null anymore - this may require
some refactoring in each case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234042 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 19:41:44 +00:00
Andrew Kaylor
675e22e7ad [WinEH] Handle nested landing pads in outlined catch handlers
Differential Revision: http://reviews.llvm.org/D8596



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234041 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 19:37:50 +00:00
Duncan P. N. Exon Smith
f4f021c0a4 CodeGen: Assert that inlined-at locations agree
As a follow-up to r234021, assert that a debug info intrinsic variable's
`MDLocalVariable::getInlinedAt()` always matches the
`MDLocation::getInlinedAt()` of its `!dbg` attachment.

The goal here is to get rid of `MDLocalVariable::getInlinedAt()`
entirely (PR22778), but I'll let these assertions bake for a while
first.

If you have an out-of-tree backend that just broke, you're probably
attaching the wrong `DebugLoc` to a `DBG_VALUE` instruction.  The one
you want is the location that was attached to the corresponding
`@llvm.dbg.declare` or `@llvm.dbg.value` call that you started with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 19:20:26 +00:00
Reid Kleckner
36ae857dc6 [WinEH] Fold cast into assertion based on review feedback
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234034 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 18:18:06 +00:00
Matthias Braun
de6157ce1e [GraphWriter] Attempt to open .dot files with xdg-open/open first
Most desktop environments let the users specify his preferred application per
file type. On mac/linux we can use open/xdg-open for that and should try this
first before starting a heuristic search for various programs.

Differential Revision: http://reviews.llvm.org/D6534

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234031 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 17:22:36 +00:00
Duncan P. N. Exon Smith
9dcb78c676 SelectionDAG: Use specialized metadata nodes in EmitFuncArgumentDbgValue(), NFC
Use `MDLocalVariable` and `MDExpression` directly for the arguments of
`EmitFuncArgumentDbgValue()` to simplify a follow-up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234026 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 17:11:42 +00:00
Duncan P. N. Exon Smith
b0d0a65e1d Verifier: Check that inlined-at locations agree
Check that the `MDLocalVariable::getInlinedAt()` in a debug info
intrinsic's variable always matches the `MDLocation::getInlinedAt()` of
its `!dbg` attachment.

The goal here is to get rid of `MDLocalVariable::getInlinedAt()`
entirely (PR22778), since it's expensive and unnecessary, but I'll let
this verifier check bake for a while (a week maybe?) first.  I've
updated the testcases that had the wrong value for `inlinedAt:`.

This checks that things are sane in the IR, but currently things go out
of whack in a few places in the backend.  I'll follow shortly with
assertions in the backend (with code fixes).

If you have out-of-tree testcases that just started failing, here's how
I updated these ones:

 1. The verifier check gives you the basic block, function, instruction,
    and relevant metadata arguments (metadata numbering doesn't
    necessarily match the source file, unfortunately).
 2. Look at the `@llvm.dbg.*()` instruction, and compare the
    `inlinedAt:` fields of the variable argument (second `metadata`
    argument) and the `!dbg` attachment.
 3. Figure out based on the variable `scope:` chain and the functions in
    the file whether the variable has been inlined (and into what), so
    you can determine which `inlinedAt:` is actually correct.  In all of
    the in-tree testcases, the `!MDLocation()` was correct and the
    `!MDLocalVariable()` was wrong, but YMMV.
 4. Duplicate the metadata that you're going to change, and add/drop the
    `inlinedAt:` field from one of them.  Be careful that the other
    references to the same metadata node point at the correct one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234021 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 16:54:30 +00:00
Duncan P. N. Exon Smith
2d2520986e CodeGen: Fix MachineInstr::print() for DBG_VALUE
Grab the `MDLocalVariable` from the second-to-last argument; the last
argument is an `MDExpression`, and mixing them up will crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234019 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 16:23:04 +00:00
Daniel Jasper
efa23ae2a9 [MachineLICM] Small cleanup: Constify and rangeify.
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234018 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 16:19:48 +00:00
Simon Pilgrim
be149a8148 [X86] Added SSE4.2 CRC32 memory folding patterns + tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234013 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 14:24:40 +00:00
Bill Schmidt
1c4b6de5ed [PowerPC] Enable splat generation for BUILD_VECTOR with little endian
When enabling PPC64LE, I disabled some optimizations of BUILD_VECTOR
nodes for little endian because wrong results were produced.  I've
subsequently investigated and found this is due to a call to
BuildVectorSDNode::isConstantSplat that was always specifying
big-endian.  With this changed to correctly identify the target
endianness, the optimizations work as expected.

I found another case of a call to the same method with big-endian
hardcoded, in PPC::isAllNegativeZeroVector().  I discovered this was
an orphaned method with no callers, so I've just removed it.

The existing test/CodeGen/PowerPC/vec_constants.ll checks these
optimizations, so for testing I've just added a variant for little
endian.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234011 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 13:48:24 +00:00
Simon Pilgrim
e5ecd32488 [X86][3DNow] Added 3DNow! memory folding patterns + tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234008 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 11:50:30 +00:00
Simon Pilgrim
4e60da755a [DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTOR
This patch attempts to fold the shuffling of 'scalar source' inputs - BUILD_VECTOR and SCALAR_TO_VECTOR nodes - if the shuffle node is the only user. This folds away a lot of unnecessary shuffle nodes, and allows quite a bit of constant folding that was being missed.

Differential Revision: http://reviews.llvm.org/D8516

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234004 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 10:02:21 +00:00
Peter Collingbourne
c39f5dd0e2 MC: For variable symbols, maintain MCSymbol::Section as a cache.
Fixes PR19582.

Previously, when an asm assignment (.set or =) was created, we would look up
the section immediately in MCSymbol::setVariableValue. This caused symbols
to receive the wrong section if the RHS of the assignment had not been seen
yet. This had a knock-on effect in the object file emitters, causing them
to emit extra symbols, or to give symbols the wrong visibility or the wrong
section. For example, in the following asm:

.data
.Llocal:

.text
leaq .Llocal1(%rip), %rdi
.Llocal1 = .Llocal2
.Llocal2 = .Llocal

the first assignment would give .Llocal1 a null section, which would never get
fixed up by the second assignment. This would cause the ELF object file emitter
to consider .Llocal1 to be an undefined symbol and give it external linkage,
even though .Llocal1 should not have been emitted at all in the object file.

Or in the following asm:

alias_to_local = Ltmp0
Ltmp0:

the Mach-O object file emitter would give the alias_to_local symbol a n_type
of N_SECT and a n_sect of 0.  This is invalid under the Mach-O specification,
which requires N_SECT symbols to receive a non-zero section number if the
symbol is defined in a section in the object file.

https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/MachORuntime/#//apple_ref/c/tag/nlist

After this change we do not look up the section when the assignment is created,
but instead look it up on demand and store it in Section, which is treated
as a cache if the symbol is a variable symbol.

This change also fixes a bug in MCExpr::FindAssociatedSection. Previously,
if we saw a subtraction, we would return the first referenced section, even in
cases where we should have been returning the absolute pseudo-section. Now we
always return the absolute pseudo-section for expressions that subtract two
section-derived expressions. This isn't always correct (e.g. if one of the
sections ends up being laid out at an absolute address), but it's probably
the best we can do without more context.

This allows us to remove code in two places where we appear to have been
working around this bug, in MachObjectWriter::markAbsoluteVariableSymbols
and in X86AsmPrinter::EmitStartOfAsmFile.

Re-applies r233595 (aka D8586), which was reverted in r233898.

Differential Revision: http://reviews.llvm.org/D8798

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233995 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 01:46:11 +00:00
Daniel Berlin
cc6ce0857c Return iterator from BasicBlock::eraseFromParent
Summary:
Same as the last patch, but for BasicBlock
(Requires same code movement)

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233992 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 01:20:33 +00:00
Matthias Braun
67a2b82b14 ARM: Handle physreg targets in RegPair hints gracefully
Register coalescing can change the target of a RegPair hint to a
physreg, we should not crash on this. This also slightly improved the
way ARMBaseRegisterInfo::updateRegAllocHint() works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-03 00:18:38 +00:00
Reid Kleckner
0f8f086e21 [ASan] Don't use stack malloc for 32-bit functions using inline asm
This prevents us from running out of registers in the backend.

Introducing stack malloc calls prevents the backend from recognizing the
inline asm operands as stack objects. When the backend recognizes a
stack object, it doesn't need to materialize the address of the memory
in a physical register. Instead it generates a simple SP-based memory
operand. Introducing a stack malloc forces the backend to find a free
register for every memory operand. 32-bit x86 simply doesn't have enough
registers for this to succeed in most cases.

Reviewers: kcc, samsonov

Differential Revision: http://reviews.llvm.org/D8790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233979 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 21:44:55 +00:00
Reid Kleckner
7c2e691607 Fix unused variable in NDEBUG builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233978 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 21:43:22 +00:00
Jingyue Wu
6dedfc073a [SLSR] handles off bounds GEPs
Summary:
The old requirement on GEP candidates being in bounds is unnecessary.
For off-bound GEPs, we still have

  &B[i * S] = B + (i * S) * e = B + (i * e) * S

Test Plan: slsr_offbound_gep in slsr-gep.ll

Reviewers: meheff

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8809

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233949 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 21:18:32 +00:00
Reid Kleckner
df4fd4fc4e [WinEH] Make llvm.eh.actions use frameescape indices for catch params
This makes it possible to use the same representation of llvm.eh.actions
in outlined handlers as we use in the parent function because i32's are
just constants that can be copied freely between functions.

I had to add a sentinel alloca to the list of child allocas so that we
don't try to sink the catch object into the handler. Normally, one would
use nullptr for this kind of thing, but TinyPtrVector doesn't support
null elements. More than that, it's elements have to have a suitable
alignment. Therefore, I settled on this for my sentinel:

  AllocaInst *getCatchObjectSentinel() {
    return static_cast<AllocaInst *>(nullptr) + 1;
  }

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233947 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 21:13:31 +00:00
Sanjay Patel
5b93ab6cde [AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vector
Without this patch, we split the 256-bit vector into halves and produced something like:
	movzwl	(%rdi), %eax
	vmovd	%eax, %xmm0
	vxorps	%xmm1, %xmm1, %xmm1
	vblendps	$15, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]

Now, we eliminate the xor and blend because those zeros are free with the vmovd:
        movzwl  (%rdi), %eax
        vmovd   %eax, %xmm0

This should be the final fix needed to resolve PR22685:
https://llvm.org/bugs/show_bug.cgi?id=22685




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233941 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 20:21:52 +00:00
David Blaikie
19443c1bcb [opaque pointer type] API migration for GEP constant factories
Require the pointee type to be passed explicitly and assert that it is
correct. For now it's possible to pass nullptr here (and I've done so in
a few places in this patch) but eventually that will be disallowed once
all clients have been updated or removed. It'll be a long road to get
all the way there... but if you have the cahnce to update your callers
to pass the type explicitly without depending on a pointer's element
type, that would be a good thing to do soon and a necessary thing to do
eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233938 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 18:55:32 +00:00
Quentin Colombet
fa8f2103a5 [AArch64] Add a comment to make it explicit why we increased the complexity.
Follow-up of r233653.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233936 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 18:54:23 +00:00
Sanjay Patel
8765e82c83 [X86, AVX] adjust tablegen patterns to generate better code for scalar insertion into zero vector (PR23073)
For code like this:

define <8 x i32> @load_v8i32() {
  ret <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
}

We produce this AVX code:

_load_v8i32:                            ## @load_v8i32
  movl	$7, %eax
  vmovd	%eax, %xmm0
  vxorps	%ymm1, %ymm1, %ymm1
  vblendps	$1, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
  retq

There are at least 2 bugs in play here:

    We're generating a blend when a move scalar does the same job using 2 less instruction bytes (see FIXMEs).
    We're not matching an existing pattern that would eliminate the xor and blend entirely. The zero bytes are free with vmovd.

The 2nd fix involves an adjustment of "AddedComplexity" [1] and mostly masks the 1st problem.

[1] AddedComplexity has close to no documentation in the source. 
The best we have is this comment: "roughly corresponds to the number of nodes that are covered". 
It appears that x86 has bastardized this definition by inflating its values for some other
undocumented reason. For example, we have a pattern with "AddedComplexity = 400" (!). 

I searched my way to this page:
https://groups.google.com/forum/#!topic/llvm-dev/5UX-Og9M0xQ

Differential Revision: http://reviews.llvm.org/D8794



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233931 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 17:56:17 +00:00
Adam Nemet
e1aa33fb9a [LoopAccesses] Handle case when no memchecks are needed after partitioning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 17:51:57 +00:00
Vasileios Kalintiris
3fabd02ea5 [mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.
Summary:
Avoid duplicate code in Mips16FrameLowering and MipsSEFrameLowering by
providing an implementation of the eliminateCallFramePseudoInstr()
function from their base class.

Depends on D8640.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233909 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 11:09:40 +00:00
Elena Demikhovsky
4eb165220f AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233906 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 10:51:40 +00:00
Vasileios Kalintiris
91a9b15130 [mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.
Summary:
adjustStackPtr() is implemented from both MipsSEInstrInfo and
Mips16InstrInfo. It makes sense to expose this function from
MipsInstrInfo and avoid explicit casting in some cases.

Depends on D8638.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233905 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 10:42:44 +00:00
Vasileios Kalintiris
cb64898a22 [mips] Make sure that we don't adjust the stack pointer by zero amount.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233904 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 10:14:54 +00:00
Vladimir Sukharev
2278d23c53 [ARM] Rename v8.1a from "extension" to "architecture": follow-up
Corrected forgotten change to remove excess "generic-armv8.1-a" cpu

Subscribers: llvm-commits

Completion of http://reviews.llvm.org/rL233811


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233903 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 09:32:14 +00:00
Peter Collingbourne
a8432640e8 Revert r233595, "MC: For variable symbols, maintain MCSymbol::Section as a cache."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233898 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 07:02:51 +00:00
Lang Hames
2eb21d0245 [Orc] Fix local-linkage handling in the CompileOnDemand layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233895 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 05:28:10 +00:00
Philip Reames
57bea4161b [gcroot] Remove unused items from an enum
These two were never implemented for gcroot, so there's no point in keeping them around now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233892 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 05:02:16 +00:00
Philip Reames
c47a3ae7d5 Teach gcroot how to handle dynamically realigned frames
I'm playing with supporting custom stack map formats with statepoints.  While 
doing so, I noticed that the existing implementation didn't indicate inherently 
unsized frames.  This change essentially just ports the functionality that already 
exists for the default StackMaps section to custom stackmaps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 05:00:40 +00:00
Lang Hames
14ef491582 [Orc] Add support classes for inspecting and running C++ static ctor/dtors, and
use these to add support for C++ static ctors/dtors to the Orc-lazy JIT in LLI.

Replace the trivial_retval_1 regression test - the new 'hello' test is covering
strictly more code. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233885 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 04:34:45 +00:00
Craig Topper
0a4630d104 Don't print an error message when looking up the scheduling model if user specified -mcpu=help.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 04:27:50 +00:00
Alexey Samsonov
d148e322a9 Fix a bug indicated by -fsanitize=shift-exponent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233881 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 01:30:10 +00:00
Daniel Berlin
525a9598d6 Return iterator from Instruction::eraseFromParent.
Summary:
This is necessary in order to make removal while using reverse iterators work.

(See http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/084122.html)

Updates to other eraseFromParent's to come in later patches.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-02 00:03:07 +00:00
Kostya Serebryany
01055ec7e3 [fuzzer] document the -tokens flag. Also change the diagnostic output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 21:33:20 +00:00
Benjamin Kramer
a066ed09db [X86] Don't accidentally select shll $1, %eax when shrinking an immediate.
addl has higher throughput and this was needlessly picking a suboptimal
encoding causing PR23098.

I wish there was a way of doing this without further duplicating tbl-
generated patterns, but so far I haven't found one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233832 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 19:01:09 +00:00
Sanjoy Das
5436372079 [SCEV] Look at backedge dominating conditions (re-land r233447).
Summary:
This change teaches ScalarEvolution::isLoopBackedgeGuardedByCond to look
at edges within the loop body that dominate the latch.  We don't do an
exhaustive search for all possible edges, but only a quick walk up the
dom tree.

This re-lands r233447.  r233447 was reverted because it caused massive
compile-time regressions.  This change has a fix for the same issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 18:24:06 +00:00
Diego Novillo
32d9020423 Remove 4,096 loop scale limitation.
Summary:
This is part 1 of fixes to address the problems described in
https://llvm.org/bugs/show_bug.cgi?id=22719.

The restriction to limit loop scales to 4,096 does not really prevent
overflows anymore, as the underlying algorithm has changed and does
not seem to suffer from this problem.

Additionally, artificially restricting loop scales to such a low number
skews frequency information, making loops of equal hotness appear to
have very different hotness properties.

The only loops that are artificially restricted to a scale of 4096 are
infinite loops (those loops with an exit mass of 0). This prevents
infinite loops from skewing the frequencies of other regions in the CFG.

At the end of propagation, frequencies are scaled to values that take no
more than 64 bits to represent. When the range of frequencies to be
represented fits within 61 bits, it pushes up the scaling factor to a
minimum of 8 to better distinguish small frequency values. Otherwise,
small frequency values are all saturated down at 1.

Tested on x86_64.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8718

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233826 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 17:42:27 +00:00
Andrew Kaylor
6b2fe99659 Fix WinEHPrepare bug with multiple catch handlers
Differential Revision: http://reviews.llvm.org/D8682



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233824 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 17:21:25 +00:00
Vladimir Sukharev
0751793310 [ARM] Rename v8.1a from "extension" to "architecture"
v8.1a is renamed to architecture, following current entity naming approach.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233811 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 14:54:56 +00:00
Vladimir Sukharev
65f303fd0c [AArch64] Rename v8.1a from "extension" to "architecture"
v8.1a is renamed to architecture, accordingly to approaches in ARM backend.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8766


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 14:49:29 +00:00
Rafael Espindola
4eeb5e9c69 git-clang-format r233603.
Thanks to Meador Inge for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233808 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 14:44:59 +00:00
Ulrich Weigand
adf55a5a57 [SystemZ] Support transactional execution on zEC12
The zEC12 provides the transactional-execution facility.  This is exposed
to users via a set of builtin routines on other compilers.  This patch
adds LLVM support to enable those builtins.  In partciular, the patch:

- adds the transactional-execution and processor-assist facilities
- adds MC support for all instructions provided by those facilities
- adds LLVM intrinsics for those instructions and hooks them up for CodeGen
- adds CodeGen support to optimize CC return value checking

Since this is first use of target-specific intrinsics on the platform,
the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and
hooks it up in Intrinsics.td.  I've also changed Triple::getArchTypePrefix
to return "s390" instead of "systemz", since the naming convention for
GCC intrinsics uses "s390" on the platform, and it neemed more straight-
forward to use the same convention for LLVM IR intrinsics.

An associated clang patch makes the intrinsics (and command line switches)
available at the source-language level.

For reference, the transactional-execution instructions are documented
in the z/Architecture Principles of Operation for the zEC12:
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf
The associated builtins are documented in the GCC manual:
http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html


Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td
+++ llvm-head/lib/Target/SystemZ/SystemZOperators.td
@@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic       : SDTypeProf
 def SDT_ZPrefetch           : SDTypeProfile<0, 2,
                                             [SDTCisVT<0, i32>,
                                              SDTCisPtrTy<1>]>;
+def SDT_ZTBegin             : SDTypeProfile<0, 2,
+                                            [SDTCisPtrTy<0>,
+                                             SDTCisVT<1, i32>]>;
 
 //===----------------------------------------------------------------------===//
 // Node definitions
@@ -180,6 +183,15 @@ def z_prefetch          : SDNode<"System
                                  [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
                                   SDNPMemOperand]>;
 
+def z_tbegin            : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tbegin_nofloat    : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tend              : SDNode<"SystemZISD::TEND", SDTNone,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
+
 //===----------------------------------------------------------------------===//
 // Pattern fragments
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i
   let Inst{15-0}  = BD2;
 }
 
+class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<4, outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  field bits<32> SoftFail = 0;
+
+  bits<16> BD2;
+
+  let Inst{31-16} = op;
+  let Inst{15-0}  = BD2;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1362,6 +1362,60 @@ let Defs = [CC] in {
 }
 
 //===----------------------------------------------------------------------===//
+// Transactional execution
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureTransactionalExecution] in {
+  // Transaction Begin
+  let hasSideEffects = 1, mayStore = 1,
+      usesCustomInserter = 1, Defs = [CC] in {
+    def TBEGIN : InstSIL<0xE560,
+                         (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                         "tbegin\t$BD1, $I2",
+                         [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
+    def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                                [(z_tbegin_nofloat bdaddr12only:$BD1,
+                                                   imm32zx16:$I2)]>;
+    def TBEGINC : InstSIL<0xE561,
+                          (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                          "tbeginc\t$BD1, $I2",
+                          [(int_s390_tbeginc bdaddr12only:$BD1,
+                                             imm32zx16:$I2)]>;
+  }
+
+  // Transaction End
+  let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
+    def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
+
+  // Transaction Abort
+  let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
+    def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
+                       "tabort\t$BD2",
+                       [(int_s390_tabort bdaddr12only:$BD2)]>;
+
+  // Nontransactional Store
+  let hasSideEffects = 1 in
+    def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
+
+  // Extract Transaction Nesting Depth
+  let hasSideEffects = 1 in
+    def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor assist
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureProcessorAssist] in {
+  let hasSideEffects = 1, R4 = 0 in
+    def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
+                      "ppa\t$R1, $R2, $R3", []>;
+  def : Pat<(int_s390_ppa_txassist GR32:$src),
+            (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
+                 0, 1)>;
+}
+
+//===----------------------------------------------------------------------===//
 // Miscellaneous Instructions.
 //===----------------------------------------------------------------------===//
 
Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td
+++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td
@@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys
   "Assume that the miscellaneous-extensions facility is installed"
 >;
 
+def FeatureTransactionalExecution : SystemZFeature<
+  "transactional-execution", "TransactionalExecution",
+  "Assume that the transactional-execution facility is installed"
+>;
+
+def FeatureProcessorAssist : SystemZFeature<
+  "processor-assist", "ProcessorAssist",
+  "Assume that the processor-assist facility is installed"
+>;
+
 def : Processor<"generic", NoItineraries, []>;
 def : Processor<"z10", NoItineraries, []>;
 def : Processor<"z196", NoItineraries,
@@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1,
-                 FeatureMiscellaneousExtensions]>;
+                 FeatureMiscellaneousExtensions,
+                 FeatureTransactionalExecution, FeatureProcessorAssist]>;
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
+      HasTransactionalExecution(false), HasProcessorAssist(false),
       TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}
 
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
@@ -42,6 +42,8 @@ protected:
   bool HasFastSerialization;
   bool HasInterlockedAccess1;
   bool HasMiscellaneousExtensions;
+  bool HasTransactionalExecution;
+  bool HasProcessorAssist;
 
 private:
   Triple TargetTriple;
@@ -102,6 +104,12 @@ public:
     return HasMiscellaneousExtensions;
   }
 
+  // Return true if the target has the transactional-execution facility.
+  bool hasTransactionalExecution() const { return HasTransactionalExecution; }
+
+  // Return true if the target has the processor-assist facility.
+  bool hasProcessorAssist() const { return HasProcessorAssist; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Index: llvm-head/lib/Support/Triple.cpp
===================================================================
--- llvm-head.orig/lib/Support/Triple.cpp
+++ llvm-head/lib/Support/Triple.cpp
@@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar
   case sparcv9:
   case sparc:       return "sparc";
 
-  case systemz:     return "systemz";
+  case systemz:     return "s390";
 
   case x86:
   case x86_64:      return "x86";
Index: llvm-head/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm-head.orig/include/llvm/IR/Intrinsics.td
+++ llvm-head/include/llvm/IR/Intrinsics.td
@@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsR600.td"
 include "llvm/IR/IntrinsicsBPF.td"
+include "llvm/IR/IntrinsicsSystemZ.td"
Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
===================================================================
--- /dev/null
+++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
@@ -0,0 +1,46 @@
+//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the SystemZ-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Transactional-execution intrinsics
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "s390" in {
+  def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+                                  [IntrNoDuplicate]>;
+
+  def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
+                                          [llvm_ptr_ty, llvm_i32_ty],
+                                          [IntrNoDuplicate]>;
+
+  def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+                                   [IntrNoDuplicate]>;
+
+  def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
+                                  [IntrNoReturn, Throws]>;
+
+  def int_s390_tend : GCCBuiltin<"__builtin_tend">,
+                      Intrinsic<[llvm_i32_ty], []>;
+
+  def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
+                      Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+
+  def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
+                                 [IntrReadWriteArgMem]>;
+
+  def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
+                              Intrinsic<[], [llvm_i32_ty]>;
+}
+
Index: llvm-head/lib/Target/SystemZ/SystemZ.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZ.h
+++ llvm-head/lib/Target/SystemZ/SystemZ.h
@@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0       = C
 const unsigned CCMASK_TM_MSB_1       = CCMASK_2 | CCMASK_3;
 const unsigned CCMASK_TM             = CCMASK_ANY;
 
+// Condition-code mask assignments for TRANSACTION_BEGIN.
+const unsigned CCMASK_TBEGIN_STARTED       = CCMASK_0;
+const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
+const unsigned CCMASK_TBEGIN_TRANSIENT     = CCMASK_2;
+const unsigned CCMASK_TBEGIN_PERSISTENT    = CCMASK_3;
+const unsigned CCMASK_TBEGIN               = CCMASK_ANY;
+
+// Condition-code mask assignments for TRANSACTION_END.
+const unsigned CCMASK_TEND_TX   = CCMASK_0;
+const unsigned CCMASK_TEND_NOTX = CCMASK_2;
+const unsigned CCMASK_TEND      = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
+
 // The position of the low CC bit in an IPM result.
 const unsigned IPM_CC = 28;
 
Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
@@ -146,6 +146,15 @@ enum {
   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
   SERIALIZE,
 
+  // Transaction begin.  The first operand is the chain, the second
+  // the TDB pointer, and the third the immediate control field.
+  // Returns chain and glue.
+  TBEGIN,
+  TBEGIN_NOFLOAT,
+
+  // Transaction end.  Just the chain operand.  Returns chain and glue.
+  TEND,
+
   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
   // ATOMIC_LOAD_<op>.
   //
@@ -318,6 +327,7 @@ private:
   SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
   // If the last instruction before MBBI in MBB was some form of COMPARE,
   // try to replace it with a COMPARE AND BRANCH just before MBBI.
@@ -355,6 +365,10 @@ private:
   MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
                                        MachineBasicBlock *BB,
                                        unsigned Opcode) const;
+  MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
+                                          MachineBasicBlock *MBB,
+                                          unsigned Opcode,
+                                          bool NoFloat) const;
 };
 } // end namespace llvm
 
Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -20,6 +20,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/IR/Intrinsics.h"
 #include <cctype>
 
 using namespace llvm;
@@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe
   // Codes for which we want to perform some z-specific combinations.
   setTargetDAGCombine(ISD::SIGN_EXTEND);
 
+  // Handle intrinsics.
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+
   // We want to use MVC in preference to even a single load/store pair.
   MaxStoresPerMemcpy = 0;
   MaxStoresPerMemcpyOptSize = 0;
@@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai
   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
 }
 
+// Return true if Op is an intrinsic node with chain that returns the CC value
+// as its only (other) argument.  Provide the associated SystemZISD opcode and
+// the mask of valid CC values if so.
+static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
+                                      unsigned &CCValid) {
+  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  switch (Id) {
+  case Intrinsic::s390_tbegin:
+    Opcode = SystemZISD::TBEGIN;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tbegin_nofloat:
+    Opcode = SystemZISD::TBEGIN_NOFLOAT;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tend:
+    Opcode = SystemZISD::TEND;
+    CCValid = SystemZ::CCMASK_TEND;
+    return true;
+
+  default:
+    return false;
+  }
+}
+
+// Emit an intrinsic with chain with a glued value instead of its CC result.
+static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
+                                             unsigned Opcode) {
+  // Copy all operands except the intrinsic ID.
+  unsigned NumOps = Op.getNumOperands();
+  SmallVector<SDValue, 6> Ops;
+  Ops.reserve(NumOps - 1);
+  Ops.push_back(Op.getOperand(0));
+  for (unsigned I = 2; I < NumOps; ++I)
+    Ops.push_back(Op.getOperand(I));
+
+  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+  SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
+  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
+  SDValue OldChain = SDValue(Op.getNode(), 1);
+  SDValue NewChain = SDValue(Intr.getNode(), 0);
+  DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
+  return Intr;
+}
+
 // CC is a comparison that will be implemented using an integer or
 // floating-point comparison.  Return the condition code mask for
 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
@@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec
   C.CCMask = NewCCMask;
 }
 
+// Return a Comparison that tests the condition-code result of intrinsic
+// node Call against constant integer CC using comparison code Cond.
+// Opcode is the opcode of the SystemZISD operation for the intrinsic
+// and CCValid is the set of possible condition-code results.
+static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
+                                  SDValue Call, unsigned CCValid, uint64_t CC,
+                                  ISD::CondCode Cond) {
+  Comparison C(Call, SDValue());
+  C.Opcode = Opcode;
+  C.CCValid = CCValid;
+  if (Cond == ISD::SETEQ)
+    // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
+    C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
+  else if (Cond == ISD::SETNE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
+  else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
+    // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
+  else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
+  else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
+    // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
+  else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
+  else
+    llvm_unreachable("Unexpected integer comparison type");
+  C.CCMask &= CCValid;
+  return C;
+}
+
 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
                          ISD::CondCode Cond) {
+  if (CmpOp1.getOpcode() == ISD::Constant) {
+    uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
+    unsigned Opcode, CCValid;
+    if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
+        CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
+        isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
+      return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
+  }
   Comparison C(CmpOp0, CmpOp1);
   C.CCMask = CCMaskForCondCode(Cond);
   if (C.Op0.getValueType().isFloatingPoint()) {
@@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D
 
 // Emit the comparison instruction described by C.
 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
+  if (!C.Op1.getNode()) {
+    SDValue Op;
+    switch (C.Op0.getOpcode()) {
+    case ISD::INTRINSIC_W_CHAIN:
+      Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
+      break;
+    default:
+      llvm_unreachable("Invalid comparison operands");
+    }
+    return SDValue(Op.getNode(), Op->getNumValues() - 1);
+  }
   if (C.Opcode == SystemZISD::ICMP)
     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
                        DAG.getConstant(C.ICmpType, MVT::i32));
@@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC
 }
 
 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
-  SDValue Chain    = Op.getOperand(0);
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
   SDValue CmpOp0   = Op.getOperand(2);
   SDValue CmpOp1   = Op.getOperand(3);
@@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C
   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
   SDValue Glue = emitCmp(DAG, DL, C);
   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
-                     Chain, DAG.getConstant(C.CCValid, MVT::i32),
+                     Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
 }
 
@@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF
                                  Node->getMemoryVT(), Node->getMemOperand());
 }
 
+// Return an i32 that contains the value of CC immediately after After,
+// whose final operand must be MVT::Glue.
+static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
+  SDValue Glue = SDValue(After, After->getNumValues() - 1);
+  SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
+  return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
+                     DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
+}
+
+SDValue
+SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  unsigned Opcode, CCValid;
+  if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
+    assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+    SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
+    SDValue CC = getCCResult(DAG, Glued.getNode());
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
+    return SDValue();
+  }
+
+  return SDValue();
+}
+
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
@@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper
     return lowerSTACKRESTORE(Op, DAG);
   case ISD::PREFETCH:
     return lowerPREFETCH(Op, DAG);
+  case ISD::INTRINSIC_W_CHAIN:
+    return lowerINTRINSIC_W_CHAIN(Op, DAG);
   default:
     llvm_unreachable("Unexpected node to lower");
   }
@@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa
     OPCODE(SEARCH_STRING);
     OPCODE(IPM);
     OPCODE(SERIALIZE);
+    OPCODE(TBEGIN);
+    OPCODE(TBEGIN_NOFLOAT);
+    OPCODE(TEND);
     OPCODE(ATOMIC_SWAPW);
     OPCODE(ATOMIC_LOADW_ADD);
     OPCODE(ATOMIC_LOADW_SUB);
@@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper
   return DoneMBB;
 }
 
+// Update TBEGIN instruction with final opcode and register clobbers.
+MachineBasicBlock *
+SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
+                                            MachineBasicBlock *MBB,
+                                            unsigned Opcode,
+                                            bool NoFloat) const {
+  MachineFunction &MF = *MBB->getParent();
+  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
+  const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
+
+  // Update opcode.
+  MI->setDesc(TII->get(Opcode));
+
+  // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
+  // Make sure to add the corresponding GRSM bits if they are missing.
+  uint64_t Control = MI->getOperand(2).getImm();
+  static const unsigned GPRControlBit[16] = {
+    0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
+    0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
+  };
+  Control |= GPRControlBit[15];
+  if (TFI->hasFP(MF))
+    Control |= GPRControlBit[11];
+  MI->getOperand(2).setImm(Control);
+
+  // Add GPR clobbers.
+  for (int I = 0; I < 16; I++) {
+    if ((Control & GPRControlBit[I]) == 0) {
+      unsigned Reg = SystemZMC::GR64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  // Add FPR clobbers.
+  if (!NoFloat && (Control & 4) != 0) {
+    for (int I = 0; I < 16; I++) {
+      unsigned Reg = SystemZMC::FP64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  return MBB;
+}
+
 MachineBasicBlock *SystemZTargetLowering::
 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
   switch (MI->getOpcode()) {
@@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr
     return emitStringWrapper(MI, MBB, SystemZ::MVST);
   case SystemZ::SRSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::SRST);
+  case SystemZ::TBEGIN:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
+  case SystemZ::TBEGIN_nofloat:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
+  case SystemZ::TBEGINC:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
   default:
     llvm_unreachable("Unexpected instr type to insert");
   }
Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -0,0 +1,352 @@
+; Test transactional-execution intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+declare i32 @llvm.s390.tbegin(i8 *, i32)
+declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
+declare void @llvm.s390.tbeginc(i8 *, i32)
+declare i32 @llvm.s390.tend()
+declare void @llvm.s390.tabort(i64)
+declare void @llvm.s390.ntstg(i64, i64 *)
+declare i32 @llvm.s390.etnd()
+declare void @llvm.s390.ppa.txassist(i32)
+
+; TBEGIN.
+define void @test_tbegin() {
+; CHECK-LABEL: test_tbegin:
+; CHECK-NOT: stmg
+; CHECK: std %f8,
+; CHECK: std %f9,
+; CHECK: std %f10,
+; CHECK: std %f11,
+; CHECK: std %f12,
+; CHECK: std %f13,
+; CHECK: std %f14,
+; CHECK: std %f15,
+; CHECK: tbegin 0, 65292
+; CHECK: ld %f8,
+; CHECK: ld %f9,
+; CHECK: ld %f10,
+; CHECK: ld %f11,
+; CHECK: ld %f12,
+; CHECK: ld %f13,
+; CHECK: ld %f14,
+; CHECK: ld %f15,
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat).
+define void @test_tbegin_nofloat1() {
+; CHECK-LABEL: test_tbegin_nofloat1:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with integer CC return value.
+define i32 @test_tbegin_nofloat2() {
+; CHECK-LABEL: test_tbegin_nofloat2:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with implicit CC check.
+define void @test_tbegin_nofloat3(i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat3:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: jnh  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TBEGIN (nofloat) with dual CC use.
+define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat4:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with register.
+define void @test_tbegin_nofloat5(i8 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat5:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0(%r2), 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0x0f00.
+define void @test_tbegin_nofloat6() {
+; CHECK-LABEL: test_tbegin_nofloat6:
+; CHECK: stmg %r6, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 3840
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xf100.
+define void @test_tbegin_nofloat7() {
+; CHECK-LABEL: test_tbegin_nofloat7:
+; CHECK: stmg %r8, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 61696
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
+define void @test_tbegin_nofloat8() {
+; CHECK-LABEL: test_tbegin_nofloat8:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
+define void @test_tbegin_nofloat9() {
+; CHECK-LABEL: test_tbegin_nofloat9:
+; CHECK: stmg %r10, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 64256
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
+define void @test_tbegin_nofloat10(i64 %n) {
+; CHECK-LABEL: test_tbegin_nofloat10:
+; CHECK: stmg %r11, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  %buf = alloca i8, i64 %n
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGINC.
+define void @test_tbeginc() {
+; CHECK-LABEL: test_tbeginc:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbeginc 0, 65288
+; CHECK: br %r14
+  call void @llvm.s390.tbeginc(i8 *null, i32 65288)
+  ret void
+}
+
+; TEND with integer CC return value.
+define i32 @test_tend1() {
+; CHECK-LABEL: test_tend1:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  ret i32 %res
+}
+
+; TEND with implicit CC check.
+define void @test_tend3(i32 *%ptr) {
+; CHECK-LABEL: test_tend3:
+; CHECK: tend
+; CHECK: je  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TEND with dual CC use.
+define i32 @test_tend2(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tend2:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TABORT with register only.
+define void @test_tabort1(i64 %val) {
+; CHECK-LABEL: test_tabort1:
+; CHECK: tabort 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 %val)
+  ret void
+}
+
+; TABORT with immediate only.
+define void @test_tabort2(i64 %val) {
+; CHECK-LABEL: test_tabort2:
+; CHECK: tabort 1234
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 1234)
+  ret void
+}
+
+; TABORT with register + immediate.
+define void @test_tabort3(i64 %val) {
+; CHECK-LABEL: test_tabort3:
+; CHECK: tabort 1234(%r2)
+; CHECK: br %r14
+  %sum = add i64 %val, 1234
+  call void @llvm.s390.tabort(i64 %sum)
+  ret void
+}
+
+; TABORT with out-of-range immediate.
+define void @test_tabort4(i64 %val) {
+; CHECK-LABEL: test_tabort4:
+; CHECK: tabort 0({{%r[1-5]}})
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 4096)
+  ret void
+}
+
+; NTSTG with base pointer only.
+define void @test_ntstg1(i64 *%ptr, i64 %val) {
+; CHECK-LABEL: test_ntstg1:
+; CHECK: ntstg %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with base and index.
+; Check that VSTL doesn't allow an index.
+define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
+; CHECK-LABEL: test_ntstg2:
+; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
+; CHECK: ntstg %r4, 0([[REG]],%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 %index
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the highest in-range displacement.
+define void @test_ntstg3(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg3:
+; CHECK: ntstg %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range positive displacement.
+define void @test_ntstg4(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg4:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the lowest in-range displacement.
+define void @test_ntstg5(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg5:
+; CHECK: ntstg %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range negative displacement.
+define void @test_ntstg6(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg6:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; ETND.
+define i32 @test_etnd() {
+; CHECK-LABEL: test_etnd:
+; CHECK: etnd %r2
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.etnd()
+  ret i32 %res
+}
+
+; PPA (Transaction-Abort Assist)
+define void @test_ppa_txassist(i32 %val) {
+; CHECK-LABEL: test_ppa_txassist:
+; CHECK: ppa %r2, 0, 1
+; CHECK: br %r14
+  call void @llvm.s390.ppa.txassist(i32 %val)
+  ret void
+}
+
Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
@@ -3,6 +3,22 @@
 # RUN: FileCheck < %t %s
 
 #CHECK: error: invalid operand
+#CHECK: ntstg	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ntstg	%r0, 524288
+
+	ntstg	%r0, -524289
+	ntstg	%r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ppa	%r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: ppa	%r0, %r0, 16
+
+	ppa	%r0, %r0, -1
+	ppa	%r0, %r0, 16
+
+#CHECK: error: invalid operand
 #CHECK: risbgn	%r0,%r0,0,0,-1
 #CHECK: error: invalid operand
 #CHECK: risbgn	%r0,%r0,0,0,64
@@ -22,3 +38,47 @@
 	risbgn	%r0,%r0,-1,0,0
 	risbgn	%r0,%r0,256,0,0
 
+#CHECK: error: invalid operand
+#CHECK: tabort	-1
+#CHECK: error: invalid operand
+#CHECK: tabort	4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tabort	0(%r1,%r2)
+
+	tabort	-1
+	tabort	4096
+	tabort	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: tbegin	-1, 0
+#CHECK: error: invalid operand
+#CHECK: tbegin	4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbegin	0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbegin	0, -1
+#CHECK: error: invalid operand
+#CHECK: tbegin	0, 65536
+
+	tbegin	-1, 0
+	tbegin	4096, 0
+	tbegin	0(%r1,%r2), 0
+	tbegin	0, -1
+	tbegin	0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: tbeginc	-1, 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc	4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbeginc	0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc	0, -1
+#CHECK: error: invalid operand
+#CHECK: tbeginc	0, 65536
+
+	tbeginc	-1, 0
+	tbeginc	4096, 0
+	tbeginc	0(%r1,%r2), 0
+	tbeginc	0, -1
+	tbeginc	0, 65536
Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s
@@ -1,6 +1,48 @@
 # For zEC12 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s
 
+#CHECK: etnd	%r0                     # encoding: [0xb2,0xec,0x00,0x00]
+#CHECK: etnd	%r15                    # encoding: [0xb2,0xec,0x00,0xf0]
+#CHECK: etnd	%r7                     # encoding: [0xb2,0xec,0x00,0x70]
+
+	etnd	%r0
+	etnd	%r15
+	etnd	%r7
+
+#CHECK: ntstg	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
+#CHECK: ntstg	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
+#CHECK: ntstg	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
+#CHECK: ntstg	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
+#CHECK: ntstg	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
+#CHECK: ntstg	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
+#CHECK: ntstg	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
+#CHECK: ntstg	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
+
+	ntstg	%r0, -524288
+	ntstg	%r0, -1
+	ntstg	%r0, 0
+	ntstg	%r0, 1
+	ntstg	%r0, 524287
+	ntstg	%r0, 0(%r1)
+	ntstg	%r0, 0(%r15)
+	ntstg	%r0, 524287(%r1,%r15)
+	ntstg	%r0, 524287(%r15,%r1)
+	ntstg	%r15, 0
+
+#CHECK: ppa	%r0, %r0, 0             # encoding: [0xb2,0xe8,0x00,0x00]
+#CHECK: ppa	%r0, %r0, 15            # encoding: [0xb2,0xe8,0xf0,0x00]
+#CHECK: ppa	%r0, %r15, 0            # encoding: [0xb2,0xe8,0x00,0x0f]
+#CHECK: ppa	%r4, %r6, 7             # encoding: [0xb2,0xe8,0x70,0x46]
+#CHECK: ppa	%r15, %r0, 0            # encoding: [0xb2,0xe8,0x00,0xf0]
+
+	ppa	%r0, %r0, 0
+	ppa	%r0, %r0, 15
+	ppa	%r0, %r15, 0
+	ppa	%r4, %r6, 7
+	ppa	%r15, %r0, 0
+
 #CHECK: risbgn	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
 #CHECK: risbgn	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
 #CHECK: risbgn	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
@@ -17,3 +59,68 @@
 	risbgn	%r15,%r0,0,0,0
 	risbgn	%r4,%r5,6,7,8
 
+#CHECK: tabort	0                       # encoding: [0xb2,0xfc,0x00,0x00]
+#CHECK: tabort	0(%r1)                  # encoding: [0xb2,0xfc,0x10,0x00]
+#CHECK: tabort	0(%r15)                 # encoding: [0xb2,0xfc,0xf0,0x00]
+#CHECK: tabort	4095                    # encoding: [0xb2,0xfc,0x0f,0xff]
+#CHECK: tabort	4095(%r1)               # encoding: [0xb2,0xfc,0x1f,0xff]
+#CHECK: tabort	4095(%r15)              # encoding: [0xb2,0xfc,0xff,0xff]
+
+	tabort	0
+	tabort	0(%r1)
+	tabort	0(%r15)
+	tabort	4095
+	tabort	4095(%r1)
+	tabort	4095(%r15)
+
+#CHECK: tbegin	0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin	4095, 0                 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
+#CHECK: tbegin	0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin	0, 1                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
+#CHECK: tbegin	0, 32767                # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
+#CHECK: tbegin	0, 32768                # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
+#CHECK: tbegin	0, 65535                # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
+#CHECK: tbegin	0(%r1), 42              # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
+#CHECK: tbegin	0(%r15), 42             # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
+#CHECK: tbegin	4095(%r1), 42           # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
+#CHECK: tbegin	4095(%r15), 42          # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
+
+	tbegin	0, 0
+	tbegin	4095, 0
+	tbegin	0, 0
+	tbegin	0, 1
+	tbegin	0, 32767
+	tbegin	0, 32768
+	tbegin	0, 65535
+	tbegin	0(%r1), 42
+	tbegin	0(%r15), 42
+	tbegin	4095(%r1), 42
+	tbegin	4095(%r15), 42
+
+#CHECK: tbeginc	0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc	4095, 0                 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
+#CHECK: tbeginc	0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc	0, 1                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
+#CHECK: tbeginc	0, 32767                # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
+#CHECK: tbeginc	0, 32768                # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
+#CHECK: tbeginc	0, 65535                # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
+#CHECK: tbeginc	0(%r1), 42              # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
+#CHECK: tbeginc	0(%r15), 42             # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
+#CHECK: tbeginc	4095(%r1), 42           # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
+#CHECK: tbeginc	4095(%r15), 42          # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
+
+	tbeginc	0, 0
+	tbeginc	4095, 0
+	tbeginc	0, 0
+	tbeginc	0, 1
+	tbeginc	0, 32767
+	tbeginc	0, 32768
+	tbeginc	0, 65535
+	tbeginc	0(%r1), 42
+	tbeginc	0(%r15), 42
+	tbeginc	4095(%r1), 42
+	tbeginc	4095(%r15), 42
+
+#CHECK: tend                            # encoding: [0xb2,0xf8,0x00,0x00]
+
+	tend
Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s
+++ llvm-head/test/MC/SystemZ/insn-bad-z196.s
@@ -244,6 +244,11 @@
 	cxlgbr	%f0, 16, %r0, 0
 	cxlgbr	%f2, 0, %r0, 0
 
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: etnd	%r7
+
+	etnd	%r7
+
 #CHECK: error: invalid operand
 #CHECK: fidbra	%f0, 0, %f0, -1
 #CHECK: error: invalid operand
@@ -546,6 +551,16 @@
 	locr	%r0,%r0,-1
 	locr	%r0,%r0,16
 
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: ntstg	%r0, 524287(%r1,%r15)
+
+	ntstg	%r0, 524287(%r1,%r15)
+
+#CHECK: error: {{(instruction requires: processor-assist)?}}
+#CHECK: ppa	%r4, %r6, 7
+
+	ppa	%r4, %r6, 7
+
 #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
 #CHECK: risbgn	%r1, %r2, 0, 0, 0
 
@@ -690,3 +705,24 @@
 	stocg	%r0,-524289,1
 	stocg	%r0,524288,1
 	stocg	%r0,0(%r1,%r2),1
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tabort	4095(%r1)
+
+	tabort	4095(%r1)
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbegin	4095(%r1), 42
+
+	tbegin	4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbeginc	4095(%r1), 42
+
+	tbeginc	4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tend
+
+	tend
+
Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt
===================================================================
--- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt
+++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt
@@ -2503,6 +2503,15 @@
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff
 
+# CHECK: etnd %r0
+0xb2 0xec 0x00 0x00
+
+# CHECK: etnd %r15
+0xb2 0xec 0x00 0xf0
+
+# CHECK: etnd %r7
+0xb2 0xec 0x00 0x70
+
 # CHECK: fidbr %f0, 0, %f0
 0xb3 0x5f 0x00 0x00
 
@@ -6034,6 +6043,36 @@
 # CHECK: ny %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x54
 
+# CHECK: ntstg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x25
+
+# CHECK: ntstg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x25
+
+# CHECK: ntstg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x25
+
+# CHECK: ntstg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x25
+
 # CHECK: oc 0(1), 0
 0xd6 0x00 0x00 0x00 0x00 0x00
 
@@ -6346,6 +6385,21 @@
 # CHECK: popcnt %r7, %r8
 0xb9 0xe1 0x00 0x78
 
+# CHECK: ppa %r0, %r0, 0
+0xb2 0xe8 0x00 0x00
+
+# CHECK: ppa %r0, %r0, 15
+0xb2 0xe8 0xf0 0x00
+
+# CHECK: ppa %r0, %r15, 0
+0xb2 0xe8 0x00 0x0f
+
+# CHECK: ppa %r4, %r6, 7
+0xb2 0xe8 0x70 0x46
+
+# CHECK: ppa %r15, %r0, 0
+0xb2 0xe8 0x00 0xf0
+
 # CHECK: risbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x55
 
@@ -8062,6 +8116,93 @@
 # CHECK: sy %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x5b
 
+# CHECK: tabort 0
+0xb2 0xfc 0x00 0x00
+
+# CHECK: tabort 0(%r1)
+0xb2 0xfc 0x10 0x00
+
+# CHECK: tabort 0(%r15)
+0xb2 0xfc 0xf0 0x00
+
+# CHECK: tabort 4095
+0xb2 0xfc 0x0f 0xff
+
+# CHECK: tabort 4095(%r1)
+0xb2 0xfc 0x1f 0xff
+
+# CHECK: tabort 4095(%r15)
+0xb2 0xfc 0xff 0xff
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 4095, 0
+0xe5 0x60 0x0f 0xff 0x00 0x00
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 0, 1
+0xe5 0x60 0x00 0x00 0x00 0x01
+
+# CHECK: tbegin 0, 32767
+0xe5 0x60 0x00 0x00 0x7f 0xff
+
+# CHECK: tbegin 0, 32768
+0xe5 0x60 0x00 0x00 0x80 0x00
+
+# CHECK: tbegin 0, 65535
+0xe5 0x60 0x00 0x00 0xff 0xff
+
+# CHECK: tbegin 0(%r1), 42
+0xe5 0x60 0x10 0x00 0x00 0x2a
+
+# CHECK: tbegin 0(%r15), 42
+0xe5 0x60 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbegin 4095(%r1), 42
+0xe5 0x60 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbegin 4095(%r15), 42
+0xe5 0x60 0xff 0xff 0x00 0x2a
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 4095, 0
+0xe5 0x61 0x0f 0xff 0x00 0x00
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 0, 1
+0xe5 0x61 0x00 0x00 0x00 0x01
+
+# CHECK: tbeginc 0, 32767
+0xe5 0x61 0x00 0x00 0x7f 0xff
+
+# CHECK: tbeginc 0, 32768
+0xe5 0x61 0x00 0x00 0x80 0x00
+
+# CHECK: tbeginc 0, 65535
+0xe5 0x61 0x00 0x00 0xff 0xff
+
+# CHECK: tbeginc 0(%r1), 42
+0xe5 0x61 0x10 0x00 0x00 0x2a
+
+# CHECK: tbeginc 0(%r15), 42
+0xe5 0x61 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r1), 42
+0xe5 0x61 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r15), 42
+0xe5 0x61 0xff 0xff 0x00 0x2a
+
+# CHECK: tend
+0xb2 0xf8 0x00 0x00
+
 # CHECK: tm 0, 0
 0x91 0x00 0x00 0x00
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233803 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 12:51:43 +00:00
David Majnemer
b0155e0975 [WinEH] Implement support for catch-all
A catch (...) doesn't have a type descriptor.  Instead, the 'adjectives'
field has bit six set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233788 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 05:20:42 +00:00
Jiangning Liu
3ee56c2c67 Fix PR23065. Avoid optimizing bitcast of build_vector with constant input to scalar_to_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 01:52:38 +00:00
Ahmed Bougacha
252c120f4a [SimplifyLibCalls] Ignore nobuiltin/unavailable fortified libcalls.
We used to do this before refactorings around r225640.
Some clang users checked for _chk libcall availability using:
  __has_builtin(__builtin___memcpy_chk)
When compiling with -fno-builtin, this is always true.
When passing -ffreestanding/-mkernel, which both imply -fno-builtin, we
end up with fortified libcalls, which isn't acceptable in a freestanding
environment which only provides their non-fortified counterparts.

Until we change clang and/or teach external users to check for availability
differently, disregard the "nobuiltin" attribute and TLI::has.

Workaround for PR23093.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233776 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 00:45:09 +00:00
Hal Finkel
54ab6ce385 [PowerPC] FastISel can't handle i1 return values when using CR bits
Under normal circumstances, use of CR bits is disabled when running at -O0, but
it is enabled by default otherwise, and if you have optnone functions, they'll
still generally be generated with crbits turned on (because nothing else turns
them off). FastISel can't handle most things dealing with i1 values when using
CR bits, and checks for that, but was not checking the return type on
functions; we can't fast-isel function calls with i1 return values either when
using CR bits for boolean values.

Fixes PR22664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-01 00:40:48 +00:00
David Majnemer
f6fb716e0f [WinEH] ExitingScope is vacuously true if !PoppedCatches.empty()
Remove a redundant condition, no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 22:43:56 +00:00
David Majnemer
64386621ec [WinEH] Generate .xdata for catch handlers
This lets us catch exceptions in simple cases.

N.B. Things that do not work include (but are not limited to):
- Throwing from within a catch handler.
- Catching an object with a named catch parameter.
- 'CatchHigh' is fictitious, we aren't sure of its purpose.
- We aren't entirely efficient with regards to the number of EH states
  that we generate.
- IP-to-State tables are sensitive to the order of emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233767 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 22:35:44 +00:00
Sanjay Patel
ace5d1d606 typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233761 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 21:24:47 +00:00
Hal Finkel
72cce21049 [PowerPC] Don't use a vector preferred memory type at -O0
Even at -O0, we fall back to SDAG when we hit intrinsics, and if the intrinsic
is a memset/memcpy/etc. we might normally use vector types. At -O0, this is
probably not a good idea (because, if there is a bug in the lowering code,
there would be no good way to turn it off). At -O0, only use scalar preferred
types.

Related to PR22754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233755 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:56:09 +00:00
Quentin Colombet
6aebd393f0 [AArch64] Enable the codegenprepare optimization that promotes operation to form
extended loads.
Implement the related target lowering hook so that the optimization has a better
estimation of the cost of an extension.

rdar://problem/19267165


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:52:32 +00:00
Duncan P. N. Exon Smith
f067a68207 IR: Enable uniquing callbacks during MDNode::replaceWithUniqued()
Uniqued nodes have more complete registration with
`ReplaceableMetadataImpl` so that they can update themselves when
operands change.  Fix a bug where `MDNode::replaceWithUniqued()` wasn't
enabling these callbacks.

The two most obvious ways missing callbacks causes problems is that
auto-resolution fails and re-uniquing (on changed operands) just doesn't
happen.  I've added tests for both -- in both cases, I confirmed that
the final check was failing before the fix.

rdar://problem/20365935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:50:50 +00:00
Hal Finkel
20fc6ac99e [SDAG] Handle non-integer preferred memset types for non-constant values
The existing code in getMemsetValue only handled integer-preferred types when
the fill value was not a constant. Make this more robust in two ways:

  1. If the preferred type is a floating-point value, do the mul-splat trick on
     the corresponding integer type and then bitcast.
  2. If the preferred type is a vector, do the mul-splat trick on one vector
     element, and then build a vector out of them.

Fixes PR22754 (although, we should also turn off use of vector types at -O0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233749 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:35:26 +00:00
Lang Hames
83b5f345b2 [ExecutionEngine] Fix MCJIT::addGlobalMapping.
This patch fixes MCJIT::addGlobalMapping by changing the implementation of the
ExecutionEngineState class. The new implementation maintains a bidirectional
mapping between symbol names (std::strings) and addresses (uint64_ts), rather
than a mapping between Value*s and void*s.

This has fix has been made for backwards compatibility, however the strongly
preferred way to resolve unknown symbols is by writing a custom
RuntimeDyld::SymbolResolver (formerly RTDyldMemoryManager) and overriding the
findSymbol method. The addGlobalMapping method is a hangover from the legacy JIT
(which has was removed in 3.6), and may be deprecated in a future release as
part of a clean-up of the ExecutionEngine interface.

Patch by Murat Bolat. Thanks Murat!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233747 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:31:14 +00:00
Kostya Serebryany
3399e1fd73 [fuzzer] Add support for token-based fuzzing (e.g. for C++). Allow string flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233745 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 20:13:20 +00:00
Matthias Braun
8e4eaabdb8 RegAllocGreedy: Allow target to specify register class ordering.
Specify an allocation order with a register class. This is used by register
allocators with a greedy heuristic. This is usefull as it is sometimes
beneficial to color more constrained classes first.

Differential Revision: http://reviews.llvm.org/D8626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233743 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 19:57:53 +00:00
Matthias Braun
3f1ec42ec7 RegAllocGreedy: Improve live interval order in ReverseLocal mode
When allocating live intervals in linear order and all of them are local
to a single basic block you get an optimal coloring. This is also true
if you reverse the order, but it is not true if you sort live ranges
beginnings in reverse order, change to sort live range endings in
reverse order. Take the following live ranges for example:

   |---| |--------|
|----------| |-------|

They get colored suboptimally with 3 registers if you sort the live range
starting points in reverse order (but optimally with live range begins in order,
or live range ends in reverse order).

Apparently the previous strategy was intentional because of allocation
time considerations. I am having a hard time replicating these effects,
while I see substantial improvements in allocation quality with this
change.

No testcase as none of the (in tree) targets use reverse order mode.

Differential Revision: http://reviews.llvm.org/D8625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233742 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 19:57:49 +00:00
Simon Atanasyan
fcadd6d973 [Hexagon] Avoid an unused variable warning when assertions are off
No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233740 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 19:43:47 +00:00
Ulrich Weigand
a9204bb532 [SystemZ] Address review comments for r233689
Change lowerCTPOP to:
- Gracefully handle a known-zero input value
- Simplify computation of significant bit size

Thanks to Jay Foad for the review!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233736 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 19:28:50 +00:00
Sanjay Patel
1b10376319 [X86, AVX] fix zero-extending integer operand load patterns to use integer instructions
This is a follow-on to r233704 and another partial fix for PR22685:
https://llvm.org/bugs/show_bug.cgi?id=22685



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233724 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 18:43:43 +00:00
Sanjay Patel
7ea151449d [X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub-types
I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354)

It improves the v4i64 case although not optimally. This AVX codegen:

  vmovq {{.*#+}} xmm0 = mem[0],zero
  vxorpd %ymm1, %ymm1, %ymm1
  vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]

Becomes:

  vmovsd {{.*#+}} xmm0 = mem[0],zero

Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here:

    We're not handling v32i8 / v16i16.
    We're not getting the FP / int domains right for instruction selection.

But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64, 
I'm submitting this patch ahead of fixing the above.

Differential Revision: http://reviews.llvm.org/D8341



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233704 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 16:32:11 +00:00
Sanjay Patel
360fb1b93b typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233701 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 16:17:51 +00:00
Ulrich Weigand
d2b60b4674 [SystemZ] Add Analysis to required_libraries (fall-out from r233688)
Should fix build failures with cmake builds


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233700 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 15:16:13 +00:00
Krzysztof Parzyszek
4654bc762e Expand MUX instructions early on Hexagon
This time with all files included.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233696 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:35:12 +00:00
Krzysztof Parzyszek
b7c19b3cc9 Revert 233694. Weak SVN-fu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:32:32 +00:00
Krzysztof Parzyszek
af4ad2d843 Expand MUX instructions early on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:29:17 +00:00
Vladimir Sukharev
e99524cf52 [AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension
Reviewers: t.p.northover, jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8502


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:15:48 +00:00
Ulrich Weigand
cb1b3ad4e1 [SystemZ] Support RISBGN instruction on zEC12
So far, we do not yet support any instruction specific to zEC12.
Most of the facilities added with zEC12 are indeed not very useful
to compiler code generation, but there is one exception: the
miscellaneous-extensions facility provides the RISBGN instruction,
which is a variant of RISBG that does not set the condition code.

Add support for this facility, MC support for RISBGN, and CodeGen
support for prefering RISBGN over RISBG on zEC12, unless we can
actually make use of the condition code set by RISBG.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:58:17 +00:00
Ulrich Weigand
ee84973420 [SystemZ] Use POPCNT instruction on z196
We already exploit a number of instructions specific to z196,
but not yet POPCNT.  Add support for the population-count
facility, MC support for the POPCNT instruction, CodeGen
support for using POPCNT, and implement the getPopcntSupport
TargetTransformInfo hook.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:56:33 +00:00
Ulrich Weigand
64aa9d8b4c [SystemZ] Provide basic TargetTransformInfo implementation
This hooks up the TargetTransformInfo machinery for SystemZ,
and provides an implementation of getIntImmCost.

In addition, the patch adds the isLegalICmpImmediate and
isLegalAddImmediate TargetLowering overrides, and updates
a couple of test cases where we now generate slightly
better code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233688 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:52:27 +00:00
Rafael Espindola
378981499a Fix the operand encoding in the test instruction.
Fixes pr22995.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:31:55 +00:00
Ulrich Weigand
3e915977af [PowerPC] Remove TargetMachine CPU auto-detection
As was done for X86 in r206094.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233684 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:01:06 +00:00
James Molloy
369ee1b1f4 [SDAG] Move TRUNCATE splitting logic into a helper, and use
it more liberally.

SplitVecOp_TRUNCATE has logic for recursively splitting oversize vectors
that need more than one round of splitting to become legal. There are many
other ISD nodes that could benefit from this logic, so factor it out and
use it for FP_TO_UINT,FP_TO_SINT,SINT_TO_FP,UINT_TO_FP and FTRUNC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 10:20:58 +00:00
Craig Topper
cd83d5b507 [X86] Stop changing result of getHostCPUName based on whether the processor supports AVX. getHostCPUFeatures should be used instead to determine whether to support AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233674 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 06:18:31 +00:00
Craig Topper
9a7c0031de Make llc use getHostCPUFeatures when 'native' is specified for cpu.
This is necessary for x86 where not all Sandybridge, Ivybrige, Haswell, and Broadwell CPUs support AVX. Currently we modify the CPU name back to Nehalem for this case, but that turns off additional features for these CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 05:52:57 +00:00
Craig Topper
caa12e0352 [X86] Be more robust against unknown Intel family 6 models. Use feature flags to guess what it might be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 05:42:45 +00:00
Ahmed Bougacha
18128bd376 [X86] Generate MOVNT for all vector types.
We used to miss non-Q YMM integer vectors, and, non-Q/D XMM integer
vectors.
While there, change the v4i32 patterns to prefer MOVNTDQ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233668 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 03:16:51 +00:00
Alexei Starovoitov
8ffc5ca532 [bpf] mark mov instructions as ReMaterializable
loading immediate into register is cheap, so take advantage of remat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233666 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 02:49:58 +00:00
Duncan P. N. Exon Smith
6b9d1f9cee Verifier: Don't return early from verifyTypeRefs()
We'll no longer crash in the `verifyTypeRefs()` (used to be called
`verifyDebugInfo()`), so there's no reason to return early here.  Remove
the `EverBroken` member since this was the only use!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 02:37:13 +00:00
Duncan P. N. Exon Smith
35ef0ef906 Verifier: Explicitly verify type references
`verifyDebugInfo()` was doing two things:

  - Asserting on unresolved type references.
  - Calling `Verify()` functions for various types of debug info.

The `Verify()` functions have been gutted, so rename the function to
`verifyTypeRefs()` and explicitly check those.  Instead of assertions,
we get nice error messages now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233664 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 02:27:32 +00:00
Duncan P. N. Exon Smith
d3cfcf9614 Verifier: Move over DISubprogram::Verify()
Move over the remaining (somewhat complicated) check from
`DISubprogram::Verify()`.  I suspect this check could be optimized --
e.g., it would be nice not to do another full traversal here -- but it's
not exactly obvious how.  For now, just bring it over as is.

Once we have a better model for the "canonical" subprogram of a
`Function`, we should enforce that all `!dbg` attachments lead to the
canonical one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233663 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 02:09:55 +00:00
Duncan P. N. Exon Smith
81a8d62b94 DebugInfo: Rewrite llvm::getDISubprogram(), NFC
Simplify implementation of `llvm::getDISubprogram()`.  I might go
through and see how difficult it is to update the users, since this
function doesn't really seem necessary anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233662 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 02:06:28 +00:00
Duncan P. N. Exon Smith
a04d764104 DebugInfo: Hide isScopeRef() and isTypeRef() behind NDEBUG
The copies of these in `lib/IR/DebugInfo.cpp` are apparently [1] only
used in assertions now, so hide them behind `#ifndef NDEBUG`.

[1]: http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/9238

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233661 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 01:47:55 +00:00
Duncan P. N. Exon Smith
c2baee4da6 Verifier: Check reference flags in debug info
Move over checks of `&` and `&&` flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233658 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 01:28:58 +00:00
Duncan P. N. Exon Smith
c0bf4a0671 Verifier: Move more debug info checks away from Verify()
Most of these checks were already in the `Verifier` so this is more of a
cleanup.  Now almost everything is over there.

Now that require a `name:` for `MDGlobalVariable`, add a check in
`LLParser` for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 01:28:22 +00:00
Duncan P. N. Exon Smith
2f5cbb5947 Verifier: Move checks over from DIDescriptor::Verify()
Move over some more checks from `DIDescriptor::Verify()`, and change
`LLParser` to require non-null `file:` fields in compile units.

I've ignored the comment in test/Assembler/metadata-null-operands.ll
since I disagree with it.  At the time that test was written (r229960),
the debug info verifier wasn't on by default, so my comment there is in
the context of not expecting the verifier to be useful.  It is now, and
besides that, since r233394 we can check when parsing textual IR whether
an operand is null that shouldn't be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233654 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 00:47:15 +00:00
Quentin Colombet
9e5f04d219 [AArch64] Fix poor codegen for add immediate.
We used to match the register variant before the immediate when the register
argument could be implicitly zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233653 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 00:31:13 +00:00
Duncan P. N. Exon Smith
16710b289b DebugInfo: Remove LexicalBlockFile scope/context distinction
Two things here:

 1. I read `getScope()` and `getContext()` backwards in r233640.  There
    was no need for `getScopeOfScope()`.  Obviously not enough test
    coverage here (as I said in that commit, I'm going to come back to
    that), but anyway I'm reverting to the behaviour before r233640.
 2. The callers that use `DILexicalBlockFile::getContext()` don't seem
    to care about the difference.  Just have it redirect to `getScope()`
    so I can't get confused again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233650 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 00:10:37 +00:00
Eric Christopher
e2424b02b2 Replace the MCSubtargetInfo parameter with a Triple when creating
an MCInstPrinter. Update all callers and use where we wanted a Triple
previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233648 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 00:10:04 +00:00
Duncan P. N. Exon Smith
1aa1d1a46c LexicalScopes: Cleanup remaining uses of DebugLoc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233644 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:58:59 +00:00
Duncan P. N. Exon Smith
497110d1b0 DebugLoc: Remove getFromDILexicalBlock()
The only user of `DebugLoc::getFromDILexicalBlock()` was creating a new
`MDLocation` as convenient API for passing an `MDScope`.  Stop doing
that, and remove the API.  If in the future we actually *want* to create
new DebugLocs, calling `MDLexicalBlock::get()` makes more sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233643 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:47:26 +00:00
Duncan P. N. Exon Smith
62e3e389b9 LexicalScopes: Use debug info hierarchy pervasively
Pervasively use the types provided by the debug info hierarchy rather
than `MDNode` in `LexicalScopes`.

I noticed (again, I guess, based on comments in the implementation?)
that `DILexicalBlockFile::getScope()` returns something different from
`DILexicalBlockFile::getContext()`.  I created a local helper for
getting the same logic from `MDLexicalBlockFile` called
`getScopeOfScope()`.  I still don't really understand it, but I've added
some FIXMEs and I'll come back to it (I suspect the way we encode these
objects isn't really ideal).

Note that my previous commit r233610 accidentally changed behaviour in
`findLexicalScope()` -- it transitioned from a call to
`DILexicalBlockFile::getScope()` to `MDLexicalBlockFile::getScope()`
(sounds right, doesn't it?) -- so I've fixed that as a drive-by.  No
tests failed with my error, so it looks like we're missing some coverage
here... when I come back to understand the logic, I'll see if I can add
some.

Other than the fix to `findLexicalScope()`, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233640 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:21:21 +00:00
David Majnemer
23ff386e07 Silence an unused variable warning.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233639 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:14:45 +00:00
Kostya Serebryany
3506457311 Move lib/Fuzzer docs from a README.txt to a proper .rst file.
Summary:
Move lib/Fuzzer docs from a README.txt to a proper .rst file.
This change does not add any content, just formatting.

Test Plan: n/a

Reviewers: samsonov

Reviewed By: samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:05:30 +00:00
Kostya Serebryany
e6d25ad0e0 [fuzzer] when a single unit takes over 1 second to run and it is the slowest one so far, print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 23:04:35 +00:00
David Majnemer
0a8ff297ad [WinEH] Run cleanup handlers when an exception is thrown
Generate tables in the .xdata section representing what actions to take
when an exception is thrown.  This currently fills in state for
cleanups, catch handlers are still unfinished.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:58:10 +00:00
Juergen Ributzka
1c8595529b Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.
When we expand the RET_ReallyLR pseudo instruction we also need to transfer the
implicit operands.

The return register is an implicit operand and without it the liveness
calculation generates an incorrect live-out set for the patchpoint.

This fixes rdar://problem/19068476.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233635 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:45:56 +00:00
Kostya Serebryany
b0b7c53ee4 [fuzzer] print various stats in a unified way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233624 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:44:03 +00:00
Alexei Starovoitov
5ca9ec70fd [bpf] add support for bswap instructions
BPF has cpu_to_be and cpu_to_le instructions.
For now assume little endian and generate cpu_to_be for ISD::BSWAP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233620 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:40:40 +00:00
Alexei Starovoitov
adb58c18f5 [bpf] fix build
fix build broken due to r233599.
Would still need to switch to MDLocation long term.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233619 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:40:35 +00:00
Eric Christopher
910e36d7bc Rename const char *Triple argument to TT to avoid shadowing llvm::Triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233615 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:31:14 +00:00
Eric Christopher
8225e356af Remove unused MCSubtargetInfo argument from the X86 MCInstPrinter ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233614 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:16:37 +00:00
Kostya Serebryany
29c6bd6e4f DFSan-based fuzzer (proof of concept).
Summary:
This adds a simple DFSan-based (i.e. taint-guided) fuzzer mutator,
see the comments for details.

Test Plan: a test added

Reviewers: samsonov, pcc

Reviewed By: samsonov, pcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:09:51 +00:00
Eric Christopher
5bd9d1e811 Remove unused MCSubtargetInfo argument from the Sparc MCInstPrinter ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233612 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:09:43 +00:00
Eric Christopher
c94e8e8a81 Remove unused MCSubtargetInfo argument from the NVPTX MCInstPrinter ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 22:03:16 +00:00
Duncan P. N. Exon Smith
35ff67e333 LexicalScopes: Use MDLocation directly instead of DebugLoc
There's no benefit to using `DebugLoc` here.  Moreover, this will let a
follow-up commit work with `MDScope` directly instead of `DebugLoc`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:54:46 +00:00
Eric Christopher
87b7793cdc Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:52:28 +00:00
Eric Christopher
cdd8ee38ea Remove unused MCSubtargetInfo argument from the AArch64 MCInstPrinter ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:52:26 +00:00
Eric Christopher
1c60a4e36b Remove unused Target argument from MCInstPrinter ctor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:52:21 +00:00
Quentin Colombet
affc406350 [RegisterCoalescer] Fix a potential misuse of direct operand index in the
terminal rule.
Spot by code inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233606 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:50:44 +00:00
David Blaikie
25e3d2d6d3 [opaque pointer type] Change GetElementPtrInst::getIndexedType to take the pointee type
This pushes the use of PointerType::getElementType up into several
callers - I'll essentially just have to keep pushing that up the stack
until I can eliminate every call to it...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:41:43 +00:00
Rafael Espindola
a55ae077e4 Fix PR23045.
Keep a note in the materializer that we are stripping debug info so that
user doing a lazy read of the module don't hit outdated formats.

Thanks to Duncan for suggesting the fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:36:43 +00:00
Duncan P. N. Exon Smith
494ae8db19 DwarfDebug: Avoid creating new DebugLocs in the backend
Don't use `DebugLoc::getFnDebugLoc()`, which creates new `MDLocation`s,
in the backend.  We just want to grab the subprogram here anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233601 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:32:28 +00:00
Duncan P. N. Exon Smith
6d42c0084e DebugInfo: Remove dead code from old DebugLoc API
Remove old API for `DebugLoc` now that all the callers have been
updated.  If this broke your out-of-tree build, here's a quick map from
the old API to the new one:

    DebugLoc DebugLoc::getFromMDLocation(MDNode *)
      => DebugLoc::DebugLoc(MDLocation *)
      => explicit DebugLoc::DebugLoc(MDNode *) // works with broken code

    MDNode *DebugLoc::getAsMDNode(LLVMContext &)
      => MDLocation *DebugLoc::get()
      => DebugLoc::operator MDLocation *()
      => MDNode *DebugLoc::getAsMDNode() // works with broken code

    bool DebugLoc::isUnknown()
      => DebugLoc::operator MDLocation *()
          i.e.: if (MDLocation *DL = ...)
      => DebugLoc::operator bool() // works with broken code
          i.e.: if (DebugLoc DL = ...)

    void DebugLoc::getScopeAndInlinedAt(MDNode *&, MDNode *&)
      => use: MDNode *DebugLoc::getScope()
         and: MDLocation *DebugLoc::getInlinedAt()

    MDNode *DebugLoc::getScopeNode(LLVMContext &)
      => MDNode *DebugLoc::getInlinedAtScope()

    void DebugLoc::dump(LLVMContext &)
      => void DebugLoc::dump()

    void DebugLoc::getFnDebugLoc(LLVMContext &)
      => void DebugLoc::getFnDebugLoc()

    MDNode *DebugLoc::getScope(LLVMContext &)
      => MDNode *DebugLoc::getScope()

    MDNode *DebugLoc::getInlinedAt(LLVMContext &)
      => MDLocation *DebugLoc::getInlinedAt()

I've noted above the only functions that won't crash on broken code (due
to downcasting to `MDLocation`).  If your code could be dealing with
broken IR (i.e., you haven't run the verifier yet, or you've used a
temporary node that will eventually (but not yet) get RAUW'ed to an
`MDLocation`), you need to restrict yourself to those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233599 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:19:50 +00:00
Rafael Espindola
37780d81b1 Use range loops and add missing braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233598 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 21:18:36 +00:00
David Blaikie
f9ed6b05a5 [opaque pointer type] More IRBuilder::createGEP (non-inbounds) migrations: CodeGenPrepare and SimplifyLibCalls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233596 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 20:42:56 +00:00
Peter Collingbourne
07ee8d2fc1 MC: For variable symbols, maintain MCSymbol::Section as a cache.
This fixes the visibility of symbols in certain edge cases involving aliases
with multiple levels of indirection.

Fixes PR19582.

Differential Revision: http://reviews.llvm.org/D8586

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 20:41:21 +00:00
Duncan P. N. Exon Smith
f175439a2b Transforms: Use the new DebugLoc API, NFC
Update lib/Analysis and lib/Transforms to use the new `DebugLoc` API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 19:49:49 +00:00
Duncan P. N. Exon Smith
39acf8f243 IR: Use the new DebugLoc API, NFC
Update lib/IR and lib/Bitcode to use the new `DebugLoc` API.  Added an
explicit conversion to `bool` (avoiding a conversion to `MDLocation`),
since a couple of these use cases need to handle broken code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 19:40:05 +00:00
Justin Holewinski
e6d6461067 [NVPTX] Associate a minimum PTX version for each SM architecture
When a new SM architecture is introduced, it is only supported by the
current PTX version and later.  Make sure we are using at least the
minimum PTX version for the target architecture.

This also removes support for PTX ISA < 3.2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233583 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 19:30:55 +00:00
Duncan P. N. Exon Smith
3637babc4c CodeGen: Use the new DebugLoc API, NFC
Update lib/CodeGen (and lib/Target) to use the new `DebugLoc` API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 19:14:47 +00:00
Duncan P. N. Exon Smith
770661092f DebugInfo: Reflow printDebugLoc() to use early returns, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233580 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 18:45:11 +00:00
Duncan P. N. Exon Smith
d0db611445 Bitcode: Reflow code to use early continues, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233578 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 18:29:18 +00:00
Duncan P. N. Exon Smith
5ae5e64f9f SelectionDAG: Reflow code to use early returns, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233577 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 18:23:28 +00:00
Justin Holewinski
d85053fc3f [NVPTX] Add options for PTX 4.1/4.2 and SM 3.2/3.7/5.2/5.3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233575 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 18:12:50 +00:00
Duncan P. N. Exon Smith
1c13197c9f DebugInfo: Write new DebugLoc API
Rewrite `DebugLoc` with a cleaner API that reflects its current status
as a wrapper around an `MDLocation` pointer.

  - Add accessors/constructors to/from `MDLocation`.
  - Simplify construction from `MDNode`.
  - Remove unnecessary `LLVMContext` from APIs.
  - Drop some API that isn't useful any more.
  - Rewrite documentation.

Actually, I've left the old API behind temporarily at the bottom of the
class so that I can update callers in separate commits.  I'll remove it
once the callers are updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 18:07:40 +00:00
Duncan P. N. Exon Smith
3584797a17 DebugInfo: Implement MDLocation::getInlinedAtScope()
Write `MDLocation::getInlinedAtScope()` and use it to re-implement
`DebugLoc::getScopeNode()` (and simplify `DISubprogram::Verify()`).
This follows the inlined-at linked list and returns the scope of the
deepest/last location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233568 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 17:41:24 +00:00
Duncan P. N. Exon Smith
7380257f0e Verifier: Add operand checks for remaining debug info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233565 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 17:21:38 +00:00
Duncan P. N. Exon Smith
d9720a4749 DebugInfo: Simplify logic in DISubprogram::Verify(), NFC
Simplify the logic in `DISubprogram::Verify()` by using the new debug
info hierarchy directly instead of the `DebugLoc` wrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233563 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 17:06:38 +00:00
Duncan P. N. Exon Smith
a3dbc680a7 Verifier: Loosen r233559 check for 'function:' field in MDSubprogram
Stop worrying about what the `function:` field is in `MDSubprogram`,
since it could be a bitcast [1].  Just check its type and leave it at
that.

[1]: http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_build/3540/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233562 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 17:04:06 +00:00
Duncan P. N. Exon Smith
d3ec0ca17e Verifier: Add operand checks for MDLexicalBlock
Add operand checks for `MDLexicalBlock` and `MDLexicalBlockFile`.  Like
`MDLocalVariable` and `MDLocation`, these nodes always require a scope.

There was no test bitrot to fix here (just updated the serialization
tests in test/Assembler/mdlexicalblock.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233561 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 16:37:48 +00:00
Duncan P. N. Exon Smith
bd38c8d788 Verifier: Check operands of MDSubprogram nodes
Check operands of `MDSubprogram`s in the verifier, and update the
accessors and factory functions to use more specific types.

There were a lot of broken testcases, which I fixed in r233466.  If you
have out-of-tree tests for debug info, you probably need similar changes
to the ones I made there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233559 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 16:19:15 +00:00
Yaron Keren
f88cbb8c49 Trying to fix the Hexagon and debian-fast bots arm32_neon_vcnt_upgrade.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233558 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 16:10:39 +00:00
Yaron Keren
6e92e7b09a Remove more superfluous .str() and replace std::string concatenation with Twine.
Following r233392, http://llvm.org/viewvc/llvm-project?rev=233392&view=rev.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233555 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 15:42:36 +00:00
Sanjay Patel
65e878bd80 more space; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233554 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 15:31:32 +00:00
Rafael Espindola
fd45ac4635 Save a std::string.
The group names are always symbol names, so we can use a StringRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233545 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 13:59:06 +00:00
Ulrich Weigand
5738b77176 [SystemZ] Fix LLVM crash on unoptimized code
Compiling the following function with -O0 would crash, since LLVM would
hit an assertion in getTestUnderMaskCond:

  int test(unsigned long x)
  {
    return x >= 0 && x <= 15;
  }

Fixed by detecting the case in the caller of getTestUnderMaskCond.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233541 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 13:46:59 +00:00
Ulrich Weigand
b42e01326d [SystemZ] Remove TargetMachine CPU auto-detection
As was done for X86 in r206094.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233540 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 13:46:25 +00:00
Rafael Espindola
0bd11cd898 Special case the creation of relocation sections.
These sections are never looked up and we know when have to create them. Use
that to save adding them to the regular map and avoid a symbol->string->symbol
conversion for the group symbol.

This also makes the implementation independent of the details of how unique
sections are implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 13:39:16 +00:00
Daniel Sanders
35efeb5e16 [mips] Support 9-bit offsets for the 'R' inline assembly memory constraint.
Summary:
The 'R' constraint is actually supposed to be much more complicated than
this and is defined in terms of whether it will cause macro expansion in
the assembler. 'R' is getting less useful due to architecture changes and
ought to be replaced by other constraints. We therefore implement 9-bit
offsets which will work for all subtargets and all instructions.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233537 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 13:27:25 +00:00
Daniel Jasper
a4b389c125 Revert "[SCEV] Look at backedge dominating conditions."
This leads to terribly slow compile times under MSAN. More discussion
on the commit thread of r233447.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233529 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 09:30:02 +00:00
Elena Demikhovsky
10e73aeede AVX-512: blank lines, duplicated tests, no functional changes
see comments http://reviews.llvm.org/D6835


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233528 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 09:29:28 +00:00
Elena Demikhovsky
f5f12f1e92 AVX-512: added intrinsics for VPAND, VPOR and VPXOR
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233525 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 08:30:34 +00:00
Craig Topper
8b042883dc [X86] In getHostCPUFeatures, disable xop, f16c, fma, and fma4 if OS does not support saving ymm state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233518 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:14 +00:00
Craig Topper
5ffc995ff3 [X86] Remove FeatureAES for 'corei7' CPU. 'corei7' should match 'nehalem' which doesn't have AES. Having AES and not PCLMUL makes 'corei7' halfway between Nehalem and Westmere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233517 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:11 +00:00
Craig Topper
c637444fed [X86] Use the more specific CPU names like 'nehalem', 'westmere', 'haswell', etc. Split Nehalem and Westmere CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233516 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:09 +00:00
Craig Topper
44f1dccd64 [X86] Move family 6 model 21 to 'pentium-m'. Near as I can tell this is a Dothan based SOC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233515 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:06 +00:00
Craig Topper
e82327a6ab [X86] Family 6 model 29 is a Penryn based processor not a Nehalem based processor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:03 +00:00
Alexei Starovoitov
1899f89632 [MCJIT] In debug memory dump output, don't truncate 64 bit addresses
Summary: In dumpMemorySections a cast was too short, and in resolveRelocations a format string was too short.

Test Plan:
Enable debug build and run a program which invokes MCJIT::finalizeObject(). Saw valid input as below (highlighted addresses were previously truncated):

```
Parse relocations:
Resolving relocations Section #0	**0x7f4c1337b000**
----- Contents of section socket1 before relocations -----
**0x00007f4c1337b000**: 18 01 00 00 01 01 01 0a 00 00 00 00 04 03 02 01
0x00007f4c1337b010: 7b 1a f8 ff 00 00 00 00 18 11 00 00 05 00 00 00

```

Reviewers: lhames

Reviewed By: lhames

Subscribers: llvm-commits, ast

Differential Revision: http://reviews.llvm.org/D8681

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233512 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 05:15:57 +00:00
Lang Hames
da62155c11 [MCJIT][Orc] Refactor RTDyldMemoryManager, weave RuntimeDyld::SymbolInfo through
MCJIT.

This patch decouples the two responsibilities of the RTDyldMemoryManager class,
memory management and symbol resolution, into two new classes:
RuntimeDyld::MemoryManager and RuntimeDyld::SymbolResolver.

The symbol resolution interface is modified slightly, from:

  uint64_t getSymbolAddress(const std::string &Name);

to:

  RuntimeDyld::SymbolInfo findSymbol(const std::string &Name);

The latter passes symbol flags along with symbol addresses, allowing RuntimeDyld
and others to reason about non-strong/non-exported symbols.


The memory management interface removes the following method:

  void notifyObjectLoaded(ExecutionEngine *EE,
                          const object::ObjectFile &) {}

as it is not related to memory management. (Note: Backwards compatibility *is*
maintained for this method in MCJIT and OrcMCJITReplacement, see below).


The RTDyldMemoryManager class remains in-tree for backwards compatibility.
It inherits directly from RuntimeDyld::SymbolResolver, and indirectly from
RuntimeDyld::MemoryManager via the new MCJITMemoryManager class, which
just subclasses RuntimeDyld::MemoryManager and reintroduces the
notifyObjectLoaded method for backwards compatibility).

The EngineBuilder class retains the existing method:

  EngineBuilder&
  setMCJITMemoryManager(std::unique_ptr<RTDyldMemoryManager> mcjmm);

and includes two new methods:

  EngineBuilder&
  setMemoryManager(std::unique_ptr<MCJITMemoryManager> MM);

  EngineBuilder&
  setSymbolResolver(std::unique_ptr<RuntimeDyld::SymbolResolver> SR);

Clients should use EITHER:

A single call to setMCJITMemoryManager with an RTDyldMemoryManager.

OR (exclusive)

One call each to each of setMemoryManager and setSymbolResolver.

This patch should be fully compatible with existing uses of RTDyldMemoryManager.
If it is not it should be considered a bug, and the patch either fixed or
reverted.

If clients find the new API to be an improvement the goal will be to deprecate
and eventually remove the RTDyldMemoryManager class in favor of the new classes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 03:37:06 +00:00
Benjamin Kramer
19d058836a Silence sign compare warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233502 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 20:49:03 +00:00
Benjamin Kramer
155328790b [inline asm] Don't reject duplicated matching constraints
They're harmless and it's easy to generate them from clang, leading to
a crash in LLVM. Found by afl-fuzz.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 20:33:07 +00:00
Simon Pilgrim
041c54b85e Use SDValue bool check to tidyup some possible vector folding ops. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233498 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 19:13:40 +00:00
Simon Pilgrim
6ff57a59a3 Use SDValue bool check to tidyup some possible ReassociateOps. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233495 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 16:49:51 +00:00
Elena Demikhovsky
a8f971683a AVX-512: Fixed the "commutative" property flag in VPANDN instruction
By Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233489 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 09:14:29 +00:00
Craig Topper
f46232d70d Fix a variable name in MSVC specific part of rr233487.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233488 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 01:07:57 +00:00
Craig Topper
87f3799e56 [X86] Implement getHostCPUFeatures for X86.
Plan to use this as part of CPU 'native' support so we can stop picking a different CPU name if CPU doesn't support AVX or AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233487 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 01:00:23 +00:00
Akira Hatanaka
971af2987a Delete MCInstPrinter::AvailableFeatures.
All the ports have been fixed to read the feature bits from the subtarget passed
to the print methods. Also, delete the call to setAvailableFeatures in the
constructor of NVPTX's instprinter as the instprinter wasn't using the feature
bits anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233486 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 21:07:24 +00:00
Akira Hatanaka
e03685b10a [X86] Read the feature bits from the subtarget that is passed to printInst
instead of from MCInstPrinter::AvailableFeatures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233485 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 20:56:05 +00:00
Hal Finkel
2eaf50f5fb [PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions
The asm syntax for the 32-bit rotate-and-mask instructions can take a 32-bit
bitmask instead of an (mb, me) pair. This syntax is not specified in the Power
ISA manual, but is accepted by GNU as, and is documented in IBM's Assembler
Language Reference. The GNU Multiple Precision Arithmetic Library (gmp)
contains assembly that uses this syntax.

To implement this, I moved the isRunOfOnes utility function from
PPCISelDAGToDAG.cpp to PPCMCTargetDesc.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233483 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 19:42:41 +00:00
Simon Pilgrim
f702ac373f [DAGCombiner] Fixed incorrect test for buildvector of constant integers.
DAGCombiner::ReassociateOps was correctly testing for an constant integer scalar but failed to correctly test for constant integer vectors (it was testing for any constant vector).

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2015-03-28 18:31:31 +00:00
Hal Finkel
8360002904 [ConstantFold] Don't fold ppc_fp128 <-> int bitcasts
PPC_FP128 is really the sum of two consecutive doubles, where the first double
is always stored first in memory, regardless of the target endianness. The
memory layout of i128, however, depends on the target endianness, and so we
can't fold this without target endianness information. As a result, we must not
do this folding in lib/IR/ConstantFold.cpp (it could be done instead in
Analysis/ConstantFolding.cpp, but that's not done now).

Fixes PR23026.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 16:44:57 +00:00
Craig Topper
5ce6ef629e Convert feature strings to lowercase even if they have a '+'/'-' in front of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233475 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 04:59:14 +00:00
Akira Hatanaka
bcdb993025 Partially revert the changes I made in r233473 to keep the code concise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233474 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 04:40:43 +00:00
Akira Hatanaka
c74135ba1b clang-format X86ATTInstPrinter.{h,cpp} before I make changes to these files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233473 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 04:25:41 +00:00
Akira Hatanaka
2841bc6858 [SparcInstPrinter] Use the subtarget that is passed to the print function
instead of the one passed to the constructor.

Unfortunately, I don't have a test case for this change. In order to test my
change, I will have to run the code after line 90 in printSparcAliasInstr. I
couldn't make that happen because printAliasInstr would always handle the
printing of fcmp instructions that the code after line 90 is supposed to handle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233471 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 04:03:51 +00:00
Craig Topper
74381e237b Update comment to match code behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233470 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 03:24:19 +00:00
Duncan P. N. Exon Smith
cefca10039 Verifier: Allow subroutine types to have no type array
Loosen one check from r233446: as long as `DIBuilder` requires a
non-null type for every subprogram, we should allow a null type array.
Also add tests for the rest of `MDSubroutineType`, which were somehow
missing.

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2015-03-28 02:43:53 +00:00
Ahmed Bougacha
44c1c890e4 [CodeGen] "PromoteInteger" f32 to f64 doesn't make sense.
The original f32->f64 promotion logic was refactored into roughly the
currently shape in r37781. However, starting with r132263, the
legalizer has been split into different kinds, and the previous
"Promote" (which did the right thing) was search-and-replace'd into
"PromoteInteger". The divide gradually deepened, with type legalization
("PromoteInteger") being separated from ops legalization
("Promote", which still works for floating point ops).

Fast-forward to today: there's no in-tree target with legal f64 but
illegal f32 (rather: no tests were harmed in the making of this patch).

With such a target, i.e., if you trick the legalizer into going through
the PromoteInteger path for FP, you get the expected brokenness.
For instance, there's no PromoteIntRes_FADD (the name itself sounds
wrong), so we'll just hit some assert in the PromoteInteger path.

Don't pretend we can promote f32 to f64. Instead, always soften.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233464 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28 01:22:37 +00:00
Akira Hatanaka
57e9efecb0 [ARM] Enable changing instprinter's behavior based on the per-function
subtarget.


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2015-03-27 23:41:42 +00:00
Akira Hatanaka
4bb318dc49 clang-format ARMInstPrinter.{h,cpp} before I make changes to these files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233448 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 23:24:22 +00:00
Sanjoy Das
e464bbfb5a [SCEV] Look at backedge dominating conditions.
Summary:
This change teaches ScalarEvolution::isLoopBackedgeGuardedByCond to look
at edges within the loop body that dominate the latch.  We don't do an
exhaustive search for all possible edges, but only a quick walk up the
dom tree.

Reviewers: atrick, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8627

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233447 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 23:18:08 +00:00
Duncan P. N. Exon Smith
b943370653 Verifier: Check operands of MDType subclasses and MDCompileUnit
Add verify checks for `MDType` subclasses and for `MDCompileUnit`.
These new checks don't yet incorporate everything from `Verify()`, but
at least they sanity check the operands.  Also downcast accessors as
possible.

A lot of these accessors can't be downcast as far as we'd like because
of arrays of typed objects (stored in a generic `MDTuple`) and
`MDString`-based type references.  Eventually I'll port over `DIRef<>`
and `DITypedArray<>` from `DebugInfo.h` to clean those up as well.

Updated bitrotted testcases separately in r233415 and r233443 to reduce
churn on the off-chance this needs to be reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233446 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 23:05:04 +00:00
Duncan P. N. Exon Smith
6ed3a762fc DebugInfo: Require non-null in DIBuilder::retainType()
Assert that a non-null value is being passed in.  Note that I fixed the
one offender in clang in r233443.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233445 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 23:00:49 +00:00
Andrew Kaylor
292142ec8d Fixing a bug with optimized catch-all handlers in WinEHPrepare
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233439 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 22:31:12 +00:00
Sanjay Patel
1f4cf39fbe fix typo and 80-col; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233427 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 21:45:18 +00:00
Rafael Espindola
0ac75919e1 Add two small structs for readability in place of std::pair and std::tuple. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233422 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 21:34:24 +00:00
David Blaikie
0e622b4f88 Constrain the type of a parameter now that callers without this constraint have been removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233419 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 20:56:11 +00:00