Jim Grosbach
8e3c17aabf
ARM: tblgen'erate more NEON two-operand aliases.
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VMUL and VEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 23:46:33 +00:00
Jim Grosbach
d83c9ea7d1
ARM: tblgen'erate more NEON two-operand aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 23:30:14 +00:00
Jim Grosbach
d8b3ed8f25
ARM: Update NEON assembly two-operand aliases.
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Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 18:12:54 +00:00
Gabor Greif
413ca0d34b
effectively back out my last change (r155190)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 11:41:38 +00:00
Gabor Greif
c77d6781d5
fix obviously bogus (IMO) operand index of the load in asserts
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(load only has one operand) and smuggle in some whitespace changes too
NB: I am obviously testing the water here, and believe that the unguarded
cast is still wrong, but why is the getZExtValue of the load's operand
tested against zero here? Any review is appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 08:58:49 +00:00
Craig Topper
420761a0f1
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 07:30:17 +00:00
Craig Topper
c909950c38
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 06:31:50 +00:00
Jim Grosbach
181b147975
ARM some VFP tblgen'erated two-operand aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 00:15:00 +00:00
Jim Grosbach
2a22b691b6
ARM let TableGen handle a few two-operand aliases.
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No need for these explicit aliases anymore. Nuke 'em.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 23:59:26 +00:00
Gabor Greif
a4b00b2db7
zap tabs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 15:16:31 +00:00
Kevin Enderby
c007eff536
Fixed the llvm-mv X86 disassembler so the 'C' API gets jumps properly
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symbolicated. These have and operand type of TYPE_RELv which was not handled
as isBranch in translateImmediate() in X86Disassembler.cpp. rdar://11268426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 23:12:11 +00:00
Chandler Carruth
37097623bb
This reverts a long string of commits to the Hexagon backend. These
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commits have had several major issues pointed out in review, and those
issues are not being addressed in a timely fashion. Furthermore, this
was all committed leading up to the v3.1 branch, and we don't need piles
of code with outstanding issues in the branch.
It is possible that not all of these commits were necessary to revert to
get us back to a green state, but I'm going to let the Hexagon
maintainer sort that out. They can recommit, in order, after addressing
the feedback.
Reverted commits, with some notes:
Primary commit r154616: HexagonPacketizer
- There are lots of review comments here. This is the primary reason
for reverting. In particular, it introduced large amount of warnings
due to a bad construct in tablegen.
- Follow-up commits that should be folded back into this when
reposting:
- r154622: CMake fixes
- r154660: Fix numerous build warnings in release builds.
- Please don't resubmit this until the three commits above are
included, and the issues in review addressed.
Primary commit r154695: Pass to replace transfer/copy ...
- Reverted to minimize merge conflicts. I'm not aware of specific
issues with this patch.
Primary commit r154703: New Value Jump.
- Primarily reverted due to merge conflicts.
- Follow-up commits that should be folded back into this when
reposting:
- r154703: Remove iostream usage
- r154758: Fix CMake builds
- r154759: Fix build warnings in release builds
- Please incorporate these fixes and and review feedback before
resubmitting.
Primary commit r154829: Hexagon V5 (floating point) support.
- Primarily reverted due to merge conflicts.
- Follow-up commits that should be folded back into this when
reposting:
- r154841: Remove unused variable (fixing build warnings)
There are also accompanying Clang commits that will be reverted for
consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 21:31:19 +00:00
Akira Hatanaka
a69534912d
Mark instruction classes ArithLogicR, ArithLogicI and LoadUpper as isRematerializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:52:10 +00:00
Akira Hatanaka
9853b49f61
Delete blank line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:47:17 +00:00
Silviu Baranga
35ee7d28a6
Added support for disassembling unpredictable swp/swpb ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:18:57 +00:00
Silviu Baranga
6b9f97dd89
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:09:07 +00:00
Silviu Baranga
fa1ebc6abe
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:12:50 +00:00
Silviu Baranga
e546c4c9c3
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:02:55 +00:00
Silviu Baranga
9e71231309
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 12:48:43 +00:00
Craig Topper
a963c81819
Remove AVX vpermil intrinsics. I removed their uses from clang headers and builtins a while back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 05:24:00 +00:00
Joe Groff
d5bda5ec66
fix pr12559: mark unavailable win32 math libcalls
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also fix SimplifyLibCalls to use TLI rather than compile-time conditionals to enable optimizations on floor, ceil, round, rint, and nearbyint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 23:05:54 +00:00
Chad Rosier
3f5966b85e
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 21:48:36 +00:00
Akira Hatanaka
b90757078f
Delete latter half of CMakeLists.txt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 18:18:09 +00:00
Akira Hatanaka
ecdc9d5bb2
Add disassembler to MIPS.
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Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 18:03:21 +00:00
Jay Foad
ef1a3a25b3
Remove unused CCIfSubtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154921 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 11:29:05 +00:00
James Molloy
72aadc057c
Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 08:18:00 +00:00
Craig Topper
2091df3d09
Don't decode vperm2i128 or vperm2f128 into a shuffle if bit 3 or 7 of the immediate is set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 05:54:54 +00:00
Kevin Enderby
c5a2a33938
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 00:49:27 +00:00
Jim Grosbach
bf42f24e6e
ARM two-operand forms for vhadd and vhsub instructions.
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rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 23:00:25 +00:00
Preston Gurd
f23293793a
Temporarily turn off anti-dependency checking
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during Post RA scheduling in X86,
until the X86 target is changed to properly set up
post RA liveness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 22:52:28 +00:00
Jim Grosbach
b8768dc32d
ARM handle :lower16: and :upper16: after a '#' prefix.
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rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 21:18:46 +00:00
Richard Smith
2c651fe6f4
Fix incorrect atomics codegen introduced in r154705, and extend test to catch it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:43:53 +00:00
David Blaikie
8834559626
Remove unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:10:13 +00:00
Jim Grosbach
199366a6a6
ARM assembly two-operand forms for VRSHL.
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rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:03:16 +00:00
Akira Hatanaka
3ef7edc77a
Do not add offset in applyFixup. This has already been accounted for in Value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:00:19 +00:00
Jim Grosbach
705e2572b4
ARM two-operand aliases for VRHADD instructions.
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rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 17:14:11 +00:00
Sirish Pande
87eb92d913
Hexagon V5 (Floating Point) Support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 17:05:06 +00:00
Craig Topper
ffa6c40ecf
Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 07:13:00 +00:00
Craig Topper
9204074598
Change type profile for vpermv back to using operand type for the mask argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 06:43:40 +00:00
Craig Topper
7e9f7fbc11
Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 06:26:15 +00:00
Craig Topper
8325c11d47
Merge vpermps/vpermd and vpermpd/vpermq SD nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 00:41:45 +00:00
Craig Topper
ca9ee66e36
Fix SDTypeProfile for vpermps. The mask operand should be v8i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 00:12:20 +00:00
Craig Topper
095c528f30
Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 23:48:57 +00:00
Craig Topper
2cb1e9dc7d
Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 22:43:31 +00:00
Nadav Rotem
f16af0a053
Fix PR12529. The Vxx family of instructions are only supported by AVX.
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Use non-vex instructions for SSE4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 19:36:44 +00:00
Benjamin Kramer
362a05a635
Wire up support for diagnostic ranges in the ARMAsmParser.
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As an example, attach range info to the "invalid instruction" message:
$ clang -arch arm -c asm.c
asm.c:2:11: error: invalid instruction
__asm__("foo r0");
^
<inline asm>:1:2: note: instantiated into assembly here
foo r0
^~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 17:04:27 +00:00
Elena Demikhovsky
73c504af9d
Added VPERM optimization for AVX2 shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 11:18:59 +00:00
NAKAMURA Takumi
8a81df1b7f
HexagonCopyToCombine.cpp: Silence two warnings, -Wunused-variable, with -Asserts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 05:33:43 +00:00
NAKAMURA Takumi
8c67cf44c5
Target/Hexagon: Tweak to fix msvc build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 05:09:09 +00:00
Richard Smith
42fc29e717
Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13 22:47:00 +00:00