Commit Graph

74733 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
2df3f58a0b Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
These the methods are target-independent since they simply scan the
memory operands.  They can live in TargetInstrInfoImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:53:24 +00:00
Owen Anderson
6d74631062 Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:42:17 +00:00
Eli Friedman
2cb1dfa446 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 19:49:37 +00:00
Benjamin Kramer
08de97a5b0 Pacify virtual dtor warnings and cmake buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 19:09:02 +00:00
Benjamin Kramer
41ab14b725 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 18:56:44 +00:00
Benjamin Kramer
c13464f3c1 llvm-objdump: disassembly enhancements
- Indent simple loops
- Print unreachable blocks as .byte directives

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 18:41:34 +00:00
Benjamin Kramer
a21d813709 llvm-objdump: Use help of CFG to print assembly when --cfg is passed.
This way we can avoid printing unreachable code (data).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 18:32:12 +00:00
Devang Patel
c040529269 Simplify by creating parent first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 18:22:10 +00:00
Jakob Stoklund Olesen
66b0f515d5 Don't clobber pending ST regs when FP regs are killed.
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 17:15:43 +00:00
Bill Wendling
bf13ee1941 Clean up the grammar for the landingpad instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 08:06:05 +00:00
Bill Wendling
63012206c9 Remove unnecessary space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 08:02:48 +00:00
Bill Wendling
2905c32335 Fix typo found by John.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 07:58:58 +00:00
Chris Lattner
f4ef8db7cd strengthen up an assertion: you can't create a constant struct
with an opaque struct type, it doesn't make sense.  This should
resolve PR10473.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-07 04:18:48 +00:00
Jakob Stoklund Olesen
69145baf36 Fix typo. Thanks, Andy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-06 18:20:24 +00:00
Andrew Trick
06988bcf6a Made SCEV's UDiv expressions more canonical. When dividing a
recurrence, the initial values low bits can sometimes be ignored.

To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.

-indvars -disable-iv-rewrite now transforms

i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4

into

i = phi i4
idx = i0 >> ...
i4 = i + 4


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-06 07:00:37 +00:00
Jakob Stoklund Olesen
ccfa446450 Reject RS_Spill ranges from local splitting as well.
All new local ranges are marked as RS_New now, so there is no need to
attempt splitting of RS_Spill ranges any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 23:50:33 +00:00
Jakob Stoklund Olesen
a9c41d39d1 Only mark remainder intervals as RS_Spill after per-block splitting.
The local ranges created get to stay in the RS_New stage, just like for
local and region splitting.

This gives tryLocalSplit a bit more freedom the first time it sees one
of these new local ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 23:50:31 +00:00
Jakob Stoklund Olesen
1f8804263f Remember to update LiveDebugVariables after per-block splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 23:10:40 +00:00
Jakob Stoklund Olesen
dab35d33ae Extract per-block splitting into its own method.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 23:04:18 +00:00
Jakob Stoklund Olesen
75e28f74b0 Delete getMultiUseBlocks and splitSingleBlocks.
These functions are no longer used, and they are easily replaced with a
loop calling shouldSplitSingleBlock and splitSingleBlock.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 22:52:17 +00:00
Jakob Stoklund Olesen
b3ef7f6b97 Also use shouldSplitSingleBlock() in the fallback splitting mode.
Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go
through a SmallPtrSet any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 22:43:23 +00:00
Jakob Stoklund Olesen
2d6d86be84 Split around single instructions to enable register class inflation.
Normally, we don't create a live range for a single instruction in a
basic block, the spiller does that anyway. However, when splitting a
live range that belongs to a proper register sub-class, inserting these
extra COPY instructions completely remove the constraints from the
remainder interval, and it may be allocated from the larger super-class.

The spiller will mop up these small live ranges if we end up spilling
anyway. It calls them snippets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 22:20:45 +00:00
Jim Grosbach
0d6fac36ed ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 21:28:30 +00:00
Jakob Stoklund Olesen
f39031b360 Detect proper register sub-classes.
Some instructions require restricted register classes, but most of the
time that doesn't affect register allocation. For example, some
instructions don't work with the stack pointer, but that is a reserved
register anyway.

Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For
such a proper sub-class, the register allocator should try to enable
register class inflation since that makes more registers available for
allocation.

Make sure only legal super-classes are considered. For example, tGPR is
not a proper sub-class in Thumb mode, but in ARM mode it is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 21:28:14 +00:00
Jim Grosbach
19dec207fc ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 20:35:44 +00:00
Jim Grosbach
6fc1c08635 Add ARM LDR parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 20:33:39 +00:00
Jakob Stoklund Olesen
54cfeda745 Fix liveness computations in BranchFolding.
The old code would look at kills and defs in one pass over the
instruction operands, causing problems with this code:

  %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg
  %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg

The last instruction kills and redefines %R0, so it is still live after
the instruction.

This caused a register scavenger crash when compiling 483.xalancbmk for
armv6. I am not including a test case because it requires too much bad
luck to expose this old bug.

First you need to convince the register allocator to use %R0 twice on
the tADDrr instruction, then you have to convince BranchFolding to do
something that causes it to run the register scavenger on he bad block.

<rdar://problem/9898200>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 18:47:07 +00:00
Jim Grosbach
16578b5088 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 16:11:38 +00:00
Jim Grosbach
ca8c70b953 ARM use a dedicated printer for postidx_reg operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 15:48:21 +00:00
Bob Wilson
9a45008e91 Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 07:24:09 +00:00
Chandler Carruth
8d8fa2506d Silence unused variable warnings in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 01:08:21 +00:00
Jason W Kim
4dd963b196 Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte fixups to be added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 00:53:03 +00:00
Chandler Carruth
4147f39769 Temporarily revert r135528 which distinguishes between two copies of one
inlined variable, based on the discussion in PR10542.

This explodes the runtime of several passes down the pipeline due to
a large number of "copies" remaining live across a large function. This
only shows up with both debug and opt, but when it does it creates
a many-minute compile when self-hosting LLVM+Clang. There are several
other cases that show these types of regressions.

All of this is tracked in PR10542, and progress is being made on fixing
the issue. Once its addressed, the re-instated, but until then this
restores the performance for self-hosting and other opt+debug builds.

Devang, let me know if this causes any trouble, or impedes fixing it in
any way, and thanks for working on this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 00:51:31 +00:00
Owen Anderson
14c903a76b Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 23:18:05 +00:00
Jim Grosbach
039c2e19c4 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 23:01:30 +00:00
Jakob Stoklund Olesen
c219d191aa Count the total amount of stack space used in compiled functions.
Patch by Ivan Krasin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 21:06:09 +00:00
Devang Patel
4d3586dd23 Print DBG_VALUE variable's location info as a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 20:44:26 +00:00
Devang Patel
d9f3fc7faa Increment counter inside insertDebugValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 20:42:11 +00:00
Devang Patel
1f35b17885 We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 20:02:18 +00:00
Devang Patel
211da8f7a9 Linke NamedMDNodes after linking global values as comment suggests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 19:44:28 +00:00
Chris Lattner
0ecd825e54 allow \r's in .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 19:31:26 +00:00
Roman Divacky
2a66cea1b8 Introduce adjustFixupOffset that adjusts the fixup offset of a relocation.
This is meant to be overriden by backends. Implement an override on PowerPC
which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes
a commented out hack and enables hello world to be compiled on PowerPC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 19:08:19 +00:00
Devang Patel
ad90d3a343 Add counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:45:38 +00:00
Evan Cheng
a81388fb4a Fix an obvious type. Patch by Ivan Krasin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:40:26 +00:00
Evan Cheng
dd5663c8e4 Fix an obvious type. Patch by Ivan Krasin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:38:15 +00:00
Owen Anderson
154c41dbbc LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:24:14 +00:00
Rafael Espindola
5c4e52e496 Fix the bitwidth of the remaining fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 17:00:11 +00:00
Duncan Sands
1203486d92 Fix a place that was clearly forgotten when the type legalization
logic moved over to its own enum.  Noticed by Andrey Karpov with
the PVS-studio tool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 16:01:54 +00:00
Rafael Espindola
251a2bbfb0 print st_shndx with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 15:50:13 +00:00