Commit Graph

177 Commits

Author SHA1 Message Date
Andrew Lenharth
507a58ac9b add missing atomic intrinsic from gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-14 05:48:15 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Evan Cheng
f26ffe987c Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 08:22:04 +00:00
Evan Cheng
0ef8de30fa Fix typos and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 22:13:02 +00:00
Evan Cheng
f0df03134e Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 08:39:06 +00:00
Dan Gohman
c9f5f3f64f Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 01:58:56 +00:00
Nate Begeman
c2616e43fd Initial X86 codegen support for VSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:34:32 +00:00
Evan Cheng
ad4196b44a Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 19:56:52 +00:00
Dan Gohman
9018e836fe For now, abort when an ISD::VAARG is encountered on x86-64, rather
than silently generate invalid code.

llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 01:26:14 +00:00
Evan Cheng
d880b97257 Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 21:53:03 +00:00
Evan Cheng
7e2ff77ef0 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08 00:57:18 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Arnold Schwaighofer
30e62c098b Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:16:33 +00:00
Dan Gohman
1f13c686df Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 17:15:20 +00:00
Chris Lattner
5e764233f3 A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
  - Make LowerAsmOperandForConstraint const.
  - Make lowerXConstraint -> LowerXConstraint
  - Make LowerXConstraint return a const char* instead of taking a string byref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-26 23:02:14 +00:00
Dan Gohman
302cd54299 Remove X86_64SRet; it isn't used anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49759 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 00:24:30 +00:00
Dan Gohman
29e4bdbf27 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:55:48 +00:00
Arnold Schwaighofer
4b5324ad2c This patch corrects the handling of byval arguments for tailcall
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).

Should fix the following problems:

Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).

Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49584 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 18:11:06 +00:00
Dan Gohman
707e018423 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
Dan Gohman
7d8143f0ef Make isVectorClearMaskLegal's operand list const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49446 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09 20:09:42 +00:00
Chris Lattner
920c37afc5 remove Evan's "ugly hack" that sorta attempted to get
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48635 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-21 06:50:21 +00:00
Arnold Schwaighofer
4fe3073cfb Don't loose incoming argument registers. Fix documentation style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 16:39:45 +00:00
Chris Lattner
8e6da15e54 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
copyfromreg/copytoreg instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 21:08:41 +00:00
Scott Michel
5b8f82e35b Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 15:42:14 +00:00
Chris Lattner
afb23f48a4 rename FP_SETRESULT -> FP_SET_ST0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:08:44 +00:00
Chris Lattner
6fa2f9c636 rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:05:32 +00:00
Evan Cheng
6fd599fa69 Add a target lowering hook to control whether it's worthwhile to compress fp constant.
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 01:30:59 +00:00
Andrew Lenharth
d19189e990 64bit CAS on 32bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 01:15:49 +00:00
Andrew Lenharth
26ed8697d4 all but CAS working on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-01 21:52:34 +00:00
Arnold Schwaighofer
258bb1b8e8 Refactor according to Evan's and Anton's suggestions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47635 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26 22:21:54 +00:00
Arnold Schwaighofer
865c68188a Change the lowering of arguments for tail call optimized
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47593 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26 09:19:59 +00:00
Evan Cheng
efec751a1b - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-18 23:04:32 +00:00
Dan Gohman
977a76fbb6 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 22:28:48 +00:00
Dan Gohman
fd29e0eb06 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 00:35:47 +00:00
Nate Begeman
14d12caf1d Enable SSE4 codegen and pattern matching.
Add some notes to the README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-11 04:19:36 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Dan Gohman
1a0248690a Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
with the real FLT_ROUNDS (defined in <float.h>).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-31 00:41:03 +00:00
Evan Cheng
ff9b373e8f Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-30 18:18:23 +00:00
Evan Cheng
0d9e976ad2 Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 19:34:22 +00:00
Dale Johannesen
ba2a0b960e Handle 'X' constraint in asm's better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46485 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 02:21:21 +00:00
Evan Cheng
2928650262 Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46286 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-23 23:17:41 +00:00
Chris Lattner
3d66185ff8 make a method public
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46159 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-18 06:52:41 +00:00
Chris Lattner
78631168d1 make it more clear that this predicate only applies to scalar FP types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46058 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-16 06:24:21 +00:00
Chris Lattner
1956d15676 introduce a isTypeInSSEReg predicate, which allows us to simplify
some code.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46055 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-16 06:19:45 +00:00
Chris Lattner
da68d30d24 no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46015 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-15 21:58:22 +00:00
Anton Korobeynikov
66fac79b89 For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed
as well as PPC codegen


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46001 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-15 07:02:33 +00:00
Gordon Henriksen
86737665b8 Refactoring the x86 and x86-64 calling convention implementations,
unifying the copied algorithms and saving over 500 LOC. There should
be no functionality change, but please test on your favorite x86
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45627 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 16:56:59 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Evan Cheng
18efe269b1 Implement ctlz and cttz with bsr and bsf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45024 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-14 02:13:44 +00:00
Chris Lattner
27a6c7380f Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to 
   take and return entire NODES that need a result expanded, not just
   the value.  This allows us to handle things like READCYCLECOUNTER,
   which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
   ExpandOperationResult.  This makes the result simpler and fully 
   general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
   i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
   allowing them to work with LegalizeDAGTypes.

LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-24 07:07:01 +00:00