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33ff5aeaa8
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14208 Commits

Author SHA1 Message Date
Akira Hatanaka
33ff5aeaa8 Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:14:58 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Eli Friedman
9db817fd0c Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d Thumb2 assembly parsing and encoding for MLA and MLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:24:45 +00:00
Jim Grosbach
84d043a8b3 Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:19:28 +00:00
Jim Grosbach
1e0fff17f3 Tidy up formatting a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:17:49 +00:00
Jim Grosbach
95102265a9 Thumb2 assembly parsing and encoding for LSL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:05:38 +00:00
Jim Grosbach
d4b72de3e2 Thumb2 assembly parsing and encoding for LDRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:02:15 +00:00
Jim Grosbach
56806c2997 Thumb2 assembly parsing and encoding for LDRSHT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:01:18 +00:00
Jim Grosbach
a315a99093 Thumb2 assembly parsing and encoding for LDRSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:54:30 +00:00
Jim Grosbach
578edfbfa0 Thumb2 assembly parsing and encoding for LDRSBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:49:06 +00:00
Jim Grosbach
0811fe13d6 Thumb2 assembly parsing and encoding for LDRSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:42:40 +00:00
Jim Grosbach
95d397c3b1 Thumb2 assembly parsing and encoding for LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:13:53 +00:00
Jim Grosbach
1efd9a0e8b Shuffle a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:09:54 +00:00
Akira Hatanaka
d199d0c59c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Jim Grosbach
e3a0adf162 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 16:45:31 +00:00
Duncan Sands
73c8415d90 Mark the eh.typeid.for intrinsic as being 'const', which it is inside 
any given function.  As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 07:50:37 +00:00
Craig Topper
d3be6ecafe Add disassembler test for Intel syntax. Tests r139353. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 06:35:44 +00:00
Akira Hatanaka
ad5f0c9e73 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 01:13:27 +00:00
Devang Patel
9aee335c23 Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:59:09 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
7cf79a88c8 Reapply testcase from r139309! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:05:43 +00:00
Kevin Enderby
5afc19002e Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom 
without a base symbol that must not have a relocation entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 20:53:44 +00:00
Bruno Cardoso Lopes
caa60f15e4 Remove this crashing test, until I figure out what's going wrong here 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
814c6ced85 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:02 +00:00
Jim Grosbach
9ea33b0c03 Add tests for Thumb2 LDRB indexed addressing w/ writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 16:49:36 +00:00
Nadav Rotem
4b36e07487 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:43:23 +00:00
Nadav Rotem
cbdd2d10ba add a testcase for the previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:31:31 +00:00
Nadav Rotem
ffe3e7da84 Add X86-SSE4 codegen support for vector-select. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:11:19 +00:00
Eli Friedman
81ac8ddc67 Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139276 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 02:23:31 +00:00
Jim Grosbach
e64fb28da1 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:39:19 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
489c693f65 Thumb2 assembly parsing and encoding for LDRB(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:17:00 +00:00
Jim Grosbach
ab899c1bcc Thumb2 assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:10:15 +00:00
Jim Grosbach
8bb5a861a0 Thumb2 assembly parsing and encoding for LDRB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:41:25 +00:00
Jim Grosbach
1aedfb47f9 Thumb2 assembly parsing and encoding for LDR(literal). 
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139257 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:33:16 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
Jim Grosbach
ed1cb6defa Add tests for Thumb2 LDR(immediate) from r139254. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:06:46 +00:00
Jim Grosbach
94f914e3fd Thumb2 parsing and encoding for LDMDB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:57:53 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Eli Friedman
d5ccb0558f Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:48:32 +00:00