Commit Graph

163 Commits

Author SHA1 Message Date
Jyotsna Verma
2d3b67ec0e Use multiclass for new-value store instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 05:12:25 +00:00
NAKAMURA Takumi
60608b924d [CMake] Update dependencies to intrinsics_gen corresponding to r169711.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 05:27:15 +00:00
Matthew Curtis
ade50dc6c7 In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07 21:03:15 +00:00
Jyotsna Verma
5807fd41a7 Define new-value store instructions with base+immediate addressing mode
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 22:02:56 +00:00
Jyotsna Verma
61b632d9f7 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 19:32:03 +00:00
Matthew Curtis
73714eac00 Fix misplaced closing brace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169404 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 19:00:34 +00:00
Jyotsna Verma
e198626f87 Define store instructions with base+register offset addressing mode
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169314 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 21:58:25 +00:00
Jyotsna Verma
4b3aafb4b2 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 18:05:01 +00:00
Jyotsna Verma
9ee1ec6115 Add constant extender support to ALU32 instructions for V2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 17:12:00 +00:00
Chandler Carruth
a1514e24cc Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 07:12:27 +00:00
Jyotsna Verma
3db6676e32 Move all operand definitions into HexagonOperands.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 05:00:31 +00:00
Jyotsna Verma
3e91da24bc Move generic Hexagon subtarget information into Hexagon.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 04:29:16 +00:00
Jyotsna Verma
bfeecc1306 Define store instructions with base+immediate offset addressing mode
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 22:26:28 +00:00
Jyotsna Verma
b434a8130f Define load instructions with base+immediate offset addressing mode
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 21:13:13 +00:00
Jyotsna Verma
2ae1df7c2c Define unsigned const-ext predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169149 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 20:39:45 +00:00
Jyotsna Verma
4fa65820ba Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 20:14:38 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Jyotsna Verma
c65317b956 Define signed const-ext predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 06:54:50 +00:00
Jyotsna Verma
f432be0c62 Use multiclass for the load instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30 17:31:52 +00:00
Jyotsna Verma
b76c710aab Use multiclass for the store instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30 06:10:22 +00:00
Jyotsna Verma
65502aa5fd Use multiclass for the load instructions with 'base + register offset'
addressing mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30 04:19:09 +00:00
Jyotsna Verma
b53b791efd Use multiclass for 'transfer' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29 19:35:44 +00:00
Jyotsna Verma
61c654ce5c Define signed const-ext immediate operands and their predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168810 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28 20:58:14 +00:00
Jyotsna Verma
5c1f3d1a83 Fix comments in HexagonOperands.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26 21:56:51 +00:00
Jyotsna Verma
b546d5a30d Add new predicates for the immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:05:09 +00:00
Jyotsna Verma
81081b16ef Use one common 'let' expression to set PrintMethod for all immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168449 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 19:53:42 +00:00
Rafael Espindola
6ee1e0867d Finish the renaming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 16:56:33 +00:00
Jyotsna Verma
24d5025d8d Renamed HexagonImmediates.td -> HexagonOperands.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 16:28:18 +00:00
Jyotsna Verma
7d1b42a842 Removing some unused instruction definitions from the Hexagon backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20 22:14:23 +00:00
Jyotsna Verma
cb02fa9d7f Added multiclass for post-increment load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:38:48 +00:00
Jyotsna Verma
266c473b91 Test commit.
Add a blank line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 06:31:55 +00:00
Andrew Trick
a78d3228e8 ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 03:13:46 +00:00
Pranav Bhandarkar
8aa138c122 Use the relationship models infrastructure to add two relations - getPredOpcode
and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.

Patch by Jyotsna Verma!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01 19:13:23 +00:00
Nadav Rotem
2704834661 Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24 17:22:41 +00:00
Nadav Rotem
cbd9a19b5d Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 23:22:48 +00:00
Bob Wilson
3b9a911efc Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang.  I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.

This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 05:43:52 +00:00
Nadav Rotem
e3d0e86919 Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 22:04:55 +00:00
Andrew Trick
412cd2f813 misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:09 +00:00
Bill Wendling
6765834754 Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 07:45:08 +00:00
Micah Villmow
3574eca1b0 Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Bill Wendling
8f00ae6a3f Use new accessor methods to query for attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 06:43:21 +00:00
Sebastian Pop
1a37d7e807 TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25 20:35:36 +00:00
Sergei Larin
c6a6660c62 DAG post-process for Hexagon MI scheduler
This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 15:07:59 +00:00
Benjamin Kramer
e5c4fe568e Remove redundant private field.
clang warned about this being unused in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 12:19:58 +00:00
Andrew Trick
78e5efe1b2 Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 00:39:15 +00:00
Sergei Larin
7ae51be2a3 Add "blocked" heuristic to the Hexagon MI scheduler.
Improve AQ instruction selection in the Hexagon MI scheduler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 17:31:34 +00:00
Benjamin Kramer
a9e37c5eaf Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 21:08:01 +00:00
Benjamin Kramer
39646d96e7 MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
  asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
  without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
  that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 17:25:13 +00:00
Pranav Bhandarkar
4c3d3ecdf8 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 16:01:40 +00:00
Richard Smith
a89fb0f170 Remove redundant semicolons to fix -pedantic-errors build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 01:41:37 +00:00