Commit Graph

84596 Commits

Author SHA1 Message Date
Craig Topper
345d16ddcc Add virtual keywords for methods that override the base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 05:48:09 +00:00
Andrew Trick
7611a88b58 Cleanup sloppy code. Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 04:41:37 +00:00
Andrew Trick
2b70dfaaeb Fix a nondeterminism in the ARM assembler.
Adding arbitrary records to ARM.td would break
basic-arm-instructions.s because selection of nop vs mov r0,r0 was
ambiguous (this will be tested by a subsequent addition to ARM.td).
An imperfect but sensible fix is to give precedence to match rules
that have more constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 03:52:57 +00:00
Jush Lu
c4dc2490c4 [arm-fast-isel] Add support for ARM PIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 02:41:21 +00:00
Andrew Trick
f26e43df26 Fix ARM vector copies of overlapping register tuples.
I have tested the fix, but have not been successfull in generating
a robust unit test. This can only be exposed through particular
register assignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 01:58:55 +00:00
Andrew Trick
d79dedd458 cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 01:58:52 +00:00
NAKAMURA Takumi
68990df1f9 Create llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 01:37:57 +00:00
Jakob Stoklund Olesen
ca71c5debe Verify the tied operand flags.
WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:38:03 +00:00
Chandler Carruth
d9f3dd96b2 Enable recursing into the compiler-rt projcet with the CMake build.
This only fires if using a recent enough CMake -- compiler-rt uses a few
of the more advanced features that not everyone needs.

Please let me know if anyone sees issues with this. I'll be updating
documentation and other stuff to tell people about this.

Many thanks to Alexey for doing a ton of work to get ASan's CMake build
into a really fantastic shape. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:38:02 +00:00
Jakob Stoklund Olesen
699ac04951 Maintain a vaild isTied bit as operands are added and removed.
The isTied bit is set automatically when a tied use is added and
MCInstrDesc indicates a tied operand. The tie is broken when one of the
tied operands is removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:58 +00:00
NAKAMURA Takumi
14b5bac547 llvm/test: [CMake] Add profile_rt-shared to deps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:56 +00:00
NAKAMURA Takumi
20f09ac39a libprofile: [CMake] Let libprofile_rt be not loadable_module but shared library. Autoconf's one does so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:51 +00:00
NAKAMURA Takumi
c3c237d8be llvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.
FIXME: profile_rt.dll could be built on win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:46 +00:00
Jack Carter
f05da8ebd6 Moved input for objdump test from Mips to Inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:10:48 +00:00
Chad Rosier
4ee0808d9f Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 23:57:47 +00:00
Michael Liao
95c22a354d Add comments on the literal value used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 23:42:17 +00:00
Jim Grosbach
5da959daff LLI: move instruction cache tweaks.
Invalidate the instruction cache right before we start actually executing code, otherwise
we can miss some that came later. This is still not quite right for a truly lazilly
compiled environment, but it's closer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 23:22:30 +00:00
Manman Ren
d26200423e Profile: set branch weight metadata with data generated from profiling.
This patch implements ProfileDataLoader which loads profile data generated by
-insert-edge-profiling and updates branch weight metadata accordingly.

Patch by Alastair Murray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 22:21:25 +00:00
Jack Carter
714313b482 The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 20:07:41 +00:00
Jack Carter
fd6d165155 Some of the instructions in the Mips instruction set are revision
delimited. llvm-mc -disassemble access these through the -mattr
option.

llvm-objdump -disassemble had no such way to set the attribute so
some instructions were just not recognized for disassembly.

This patch accepts llvm-mc mechanism for specifying the attributes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 19:24:49 +00:00
Michael Liao
8e48e0b120 Explicitly update the number of nodes to be traversed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 19:20:29 +00:00
Jack Carter
69dba7e204 Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 19:07:39 +00:00
Roman Divacky
c6c2ced384 Emit word of zeroes after the last instruction as a start of the mandatory
traceback table on PowerPC64. This helps gdb handle exceptions. The other
mandatory fields are ignored by gdb and harder to implement so just add
there a FIXME.

Patch by Bill Schmidt. PR13641.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 19:06:55 +00:00
Akira Hatanaka
4fb08317af Follow-up patch to r162731.
Fix a couple of bugs in mips' long branch pass.
This patch was supposed to be committed along with r162731, so I don't have a
new test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:58:57 +00:00
Jakob Stoklund Olesen
4ba6916a98 Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:34:41 +00:00
Jakob Stoklund Olesen
190e342cbc Don't allow TargetFlags on MO_Register MachineOperands.
Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:05:48 +00:00
Bill Wendling
96da080b88 Patch by Sean Silva to un-barf his computer by explicitly removing the '\n'
character instead of always the last character.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 17:18:27 +00:00
Hal Finkel
621b77ade2 Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 16:12:39 +00:00
Benjamin Kramer
37dca6331d InstCombine: Defensively avoid undefined shifts by limiting the amount to the bit width.
No test case, undefined shifts get folded early, but can occur when other
transforms generate a constant. Thanks to Duncan for bringing this up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 13:59:23 +00:00
Benjamin Kramer
aac7c650a6 InstCombine: Guard the transform introduced in r162743 against large ints and non-const shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 13:08:13 +00:00
Nadav Rotem
a694e2a691 Make sure that we don't call getZExtValue on values > 64 bits.
Thanks Benjamin for noticing this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 12:23:22 +00:00
Nadav Rotem
9753f0b9b4 Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.
For example:
  %1 = lshr i32 %x, 2
  %2 = udiv i32 %1, 100

rdar://12182093




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 10:01:43 +00:00
Bill Wendling
eeba6e8317 The commutative flag is already correctly set within the multiclass. If we set
it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 07:36:46 +00:00
Craig Topper
d902194631 Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 07:30:47 +00:00
Craig Topper
13897fb263 Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 07:05:28 +00:00
NAKAMURA Takumi
2f820a5d64 llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 04:04:29 +00:00
Michael Liao
dbf8b5be97 Fix PR12312
- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
  Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
  X86ISD::OR node has only its flag result being used as a boolean value and
  all its leaves are extracted from the same vector, it could be folded into an
  X86ISD::PTEST node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:34:40 +00:00
Jakob Stoklund Olesen
325907d086 Check all patterns for missing instruction flags.
Both single-instruction and multi-instruction patterns can be checked
for missing mayLoad / mayStore, and hasSideEffects flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:26:49 +00:00
Jakob Stoklund Olesen
36d29bc723 Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:11:32 +00:00
Jakob Stoklund Olesen
cff9baa952 Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.

We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:11:27 +00:00
Akira Hatanaka
273956d8c6 Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:03:05 +00:00
Hal Finkel
8dc440a46a Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
 - Clearly separate load/store-with-update instructions from regular loads and stores.
 - Split IntRotateD -> IntRotateD and IntRotateDI
 - Split out fsub and fadd from FPGeneral -> FPAddSub
 - Update existing itineraries

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:49:14 +00:00
Akira Hatanaka
1d522388bf Fix bug 13532.
In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without
using any f64 operations if f64 is not a legal type.

Patch by Stefan Kristiansson. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:12:42 +00:00
Hal Finkel
f3c3828e57 Allow remat of LI on PPC.
Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:10:33 +00:00
Hal Finkel
d939cd68f4 Add the Freescale vendor to Triple.
Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow
clang support for Freescale cross-compile configurations.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:10:30 +00:00
Hal Finkel
82b3821208 Eliminate redundant CR moves on PPC32.
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:10:27 +00:00
Hal Finkel
97d047dec7 Optimize zext on PPC64.
The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:10:15 +00:00
Eric Christopher
164a308b56 Temporarily revert this to bring back the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 01:17:46 +00:00
Jakob Stoklund Olesen
2f1c6f52bd More missing mayLoad flags on AVX multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 00:02:01 +00:00
Jakob Stoklund Olesen
dd364419ee Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 23:58:52 +00:00