call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6465 91177308-0d34-0410-b5e6-96231b3b80d8
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6375 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6339 91177308-0d34-0410-b5e6-96231b3b80d8
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6265 91177308-0d34-0410-b5e6-96231b3b80d8
of them with BUildMI calls instead.
* Fix def information in instructions generated by prologepilog inserter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5287 91177308-0d34-0410-b5e6-96231b3b80d8
(2) Use intelligent multiply selection code for array allocas.
(3) Don't use cache padding for alloca'd stack slots!
(4) Bug fix in handling call arguments: was not copying sixth FP arg
to int reg. when calling a function with no prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4130 91177308-0d34-0410-b5e6-96231b3b80d8
Don't allow direct FP-to-uint conversion (must be eliminated by preselection).
Address arithmetic for arrays is now entirely 64-bit so no sign-ext needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3961 91177308-0d34-0410-b5e6-96231b3b80d8
-- A few bug fixes in casting between floats and ints.
-- Use SRL reg, 0 instead of AND reg, 0xffffffff to clear high 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3579 91177308-0d34-0410-b5e6-96231b3b80d8
SetOperandsForMemInstr significantly). Load and Store
no longer have any indices. Eliminate spurious sign-extension
on a cast to float/double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3498 91177308-0d34-0410-b5e6-96231b3b80d8
basic block.
Mark setCCInstr used as dest. of conditional-move as both a def and a use.
BA instruction no longer has the unused CC argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2836 91177308-0d34-0410-b5e6-96231b3b80d8
-- correct sign extensions for integer casts and for shift-by-constant
instructions generated for integer multiply
-- passing FP arguments to functions with more than 6 arguments
-- passing FP arguments to varargs functions
-- passing FP arguments to functions with no prototypes
-- incorrect stack frame size when padding a section
-- folding getelementptr operations with mixed array and struct indexes
-- use uint64_t instead of uint for constant offsets in mem operands
-- incorrect coloring for CC registers (both int and FP): interferences
were being completely ignored for int CC and were considered but no
spills were marked for fp CC!
Also some code improvements:
-- better interface to generating machine instr for common cases
(many places still need to be updated to use this interface)
-- annotations on MachineInstr to communicate information from
one codegen phase to another (now used to pass information about
CALL/JMPLCALL operands from selection to register allocation)
-- all sizes and offests in class TargetData are uint64_t instead of uint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2640 91177308-0d34-0410-b5e6-96231b3b80d8
