Commit Graph

193 Commits

Author SHA1 Message Date
Evan Cheng
3738f2d59f Poorly named option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47400 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-20 20:57:32 +00:00
Evan Cheng
79964fdbaf Disable for now. This is pessimizing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47354 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-20 02:29:17 +00:00
Evan Cheng
e9c608d6cc Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47351 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-19 23:36:51 +00:00
Evan Cheng
9f143ce989 Only using x86-64 rip relative addressing in non-staic mode?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47019 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 19:20:46 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Evan Cheng
be3bf42331 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
Evan Cheng
4e3f5a4e9c Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 23:06:48 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Evan Cheng
0d9e976ad2 Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 19:34:22 +00:00
Chris Lattner
d43d00cf3a Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register.  This causes significant codegen ugliness in some cases.  For 
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:

_bar:
	subl	$28, %esp
	call	L_foo$stub
	fstpl	16(%esp)
	movsd	16(%esp), %xmm0
	movsd	%xmm0, 8(%esp)
	fldl	8(%esp)
	addl	$28, %esp
	ret

because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.

Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always 
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.

This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case.  This gives 
us this code for the example above:

_bar:
	subl	$12, %esp
	call	L_foo$stub
	addl	$12, %esp
	ret

The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert).  This is gross, but
less gross than the code it is replacing :)

This also allows us to generate better code in several other cases.  For 
example on fp-stack-ret-conv.ll, we now generate:

_test:
	subl	$12, %esp
	call	L_foo$stub
	fstps	8(%esp)
	movl	16(%esp), %eax
	cvtss2sd	8(%esp), %xmm0
	movsd	%xmm0, (%eax)
	addl	$12, %esp
	ret

where before we produced (incidentally, the old bad code is identical to what
gcc produces):

_test:
	subl	$12, %esp
	call	L_foo$stub
	fstpl	(%esp)
	cvtsd2ss	(%esp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	16(%esp), %eax
	movsd	%xmm0, (%eax)
	addl	$12, %esp
	ret

Note that we generate slightly worse code on pr1505b.ll due to a scheduling 
deficiency that is unrelated to this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
Evan Cheng
b1a9aec515 Fix a x86-64 static codegen bug. This fixes a lot of x86-64 jit failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45733 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-08 02:06:11 +00:00
Evan Cheng
0475ab58b8 Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it can be moved if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45605 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 00:41:47 +00:00
Chris Lattner
84bc5427d6 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31 04:13:23 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Evan Cheng
f02ca69951 Fix JIT code emission of X86::MovePCtoStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45307 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-22 02:26:46 +00:00
Evan Cheng
1314b00cf2 Fold some and + shift in x86 addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44970 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-13 00:43:27 +00:00
Chris Lattner
5aaddaa7b8 aesthetic changes, no functionality change. Evan, it's not clear
what 'Available' is, please add a comment near it and rename it
if appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44703 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-08 07:22:58 +00:00
Chris Lattner
8a594489bf Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:

_test2:
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M1
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M2
	ret

instead of:

_test2:
	pcmpeqd	%mm0, %mm0
	movq	%mm0, _M1
	movq	%mm0, _M2
	ret

This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type.  This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.

This patch makes the following changes:

1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
   their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
   immAllZerosV in the wrong form now use *_bc to match them with a
   bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle 
   bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
   is legal, instead of generating one that is illegal and expecting
   a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.

This patch is definite goodness, but has the potential to cause random
code quality regressions.  Please be on the lookout for these and let 
me know if they happen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-25 00:24:49 +00:00
Bill Wendling
0d642871f5 Silence, accersed warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43609 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-01 08:51:44 +00:00
Dan Gohman
8368805e25 Fix the folding of multiplication into addresses on x86, which was broken
by the recent {U,S}MUL_LOHI changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43230 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-22 20:22:24 +00:00
Evan Cheng
96aaa54529 Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42894 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12 07:55:53 +00:00
Dan Gohman
74f87a63b6 Fix grammar in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42786 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-09 15:44:37 +00:00
Dan Gohman
525178cdbf Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08 18:33:35 +00:00
Anton Korobeynikov
2fe1259d0a Partly revert invalid r41774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42322 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-25 21:52:30 +00:00
Dan Gohman
a37c9f7506 When both x/y and x%y are needed (x and y both scalar integer), compute
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42308 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-25 18:23:27 +00:00
Dale Johannesen
48d1e4517e When mixing SSE and x87 codegen, it's possible to
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42281 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-24 22:52:39 +00:00
Evan Cheng
ef61ed3507 TableGen no longer emit CopyFromReg nodes for implicit results in physical
registers. The scheduler is now responsible for emitting them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41781 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 23:59:02 +00:00
Dale Johannesen
cdd509aecd Apply feedback from previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41774 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 21:07:57 +00:00
Dale Johannesen
eaf089430e Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-31 04:03:46 +00:00
Dan Gohman
badb2d23d1 When x86 addresses matching exceeds its recursion limit, check to
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41049 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-13 20:03:06 +00:00
Christopher Lamb
a1eb155e52 Use subregs to improve any_extend code generation when feasible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41013 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 22:22:41 +00:00
Christopher Lamb
c59e52108b Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 21:48:46 +00:00
Evan Cheng
f7ef26e701 divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40972 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-09 21:59:35 +00:00
Dale Johannesen
cdbe4d3ebe Long double patch 8 of N: make it partially work in
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40906 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-07 20:29:26 +00:00
Dale Johannesen
6a30811d5c Get X86 long double calling convention to work
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40877 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-06 21:31:06 +00:00
Evan Cheng
7afa166c76 Switch some multiplication instructions over to the new scheme for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40723 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 05:48:35 +00:00
Evan Cheng
f6844ca0e4 Mac OS X X86-64 low 4G address not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 23:45:51 +00:00
Christopher Lamb
2dc6dc619c Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40578 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-29 01:24:57 +00:00
Evan Cheng
cf5543c47e Minor bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40535 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 17:02:45 +00:00
Evan Cheng
518143d795 Same goes for constantpool, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 07:35:15 +00:00
Evan Cheng
a49ed78c27 Mac OS X x86-64 lower 4G address is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40502 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 23:41:36 +00:00
Dan Gohman
dc9b3d0bb5 Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40480 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-24 23:00:27 +00:00
Dale Johannesen
849f214a4e Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants.  Some factoring
improvments forthcoming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-03 00:53:03 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Chris Lattner
a1b253f58e Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35926 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 22:29:46 +00:00
Anton Korobeynikov
f6e9353e1a Oops :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35438 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 18:38:33 +00:00
Anton Korobeynikov
33bf8c44dd Don't allow MatchAddress recurse too much. This trims exponential
behaviour in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35437 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 18:36:33 +00:00
Chris Lattner
a16b7cb1d3 Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 06:08:29 +00:00
Chris Lattner
6241226b09 Fix a miscompilation in the addr mode code trying to implement X | C and
X + C to promote LEA formation.  We would incorrectly apply it in some cases
(test) and miss it in others.

This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33884 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-04 20:18:17 +00:00
Evan Cheng
706535db86 Linux GOT indirect reference is only necessary in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33441 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-22 21:34:25 +00:00