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3796015b5b
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238 Commits

Author SHA1 Message Date
Hao Liu
3796015b5b [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types. 
E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 01:38:41 +00:00
Hao Liu
0f6ebf1aa3 [AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect. 
E.g. the codegen result is 
     fmls v1.2s, v0.2s, v2.s[3]
which is expected to be
     fmls v0.2s, v1.2s, v2.s[3]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198001 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 07:12:34 +00:00
Hao Liu
dfe4fd9ceb [AArch64]Add patterns to match normal shift nodes: shl, sra and srl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197969 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 09:00:21 +00:00
Kevin Qin
4905226c1c [AArch64 NEON] Fix a bug when lowering BUILD_VECTOR. 
DAG.getVectorShuffle() doesn't always return a vector_shuffle node.
If mask is the exact sequence of it's operand(For example, operand_0
is v8i8, and  the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly
return that operand. So a check is added here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197967 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 08:16:06 +00:00
Kevin Qin
0e8c1f5ca3 [AArch64 NEON] Fix a pattern match failure with NEON_VDUP. 
This failure caused by improper condition when lowering shuffle_vector
to scalar_to_vector. After this patch NEON_VDUP with v1i64 will not
be generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197966 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 08:11:47 +00:00
Ana Pazos
25f4d51bcb [AArch64] Check fmul node single use in fused multiply patterns 
Check for single use of fmul node in fused multiply patterns
to allow generation of fused multiply add/sub instructions.
Otherwise fmul operation ends up being repeated more than
once which does not help peformance on targets with
only one MAC unit, as for example cortex-a53.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197929 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 00:47:29 +00:00
Ana Pazos
f5bfe97875 [AArch64 NEON] Fixed fused multiply negate add/sub patterns 
The correct pattern matching should be:

- fnmadd is (-Ra) + (-Rn)*Rm  which should be matched as:

  fma (fneg node:$Rn),  node:$Rm, (fneg node:$Ra) and as

  (f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm))))

- fnmsub is (-Ra) + Rn*Rm which should be matched as

  fma node:$Rn,  node:$Rm, (fneg node:$Ra) and as

  (f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra))))



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197928 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 00:40:10 +00:00
Kevin Qin
0a9ff8776b [AArch64 NEON]Implment loading vector constant form constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197551 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-18 06:26:04 +00:00
Chad Rosier
0762d6c0a7 [AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197402 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 18:29:35 +00:00
Rafael Espindola
ea53c6ae30 The preferred alignment defaults to the abi alignment. Omit if it is the same. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197400 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 18:01:51 +00:00
Rafael Espindola
7ef5520e8c On DataLayout, omit the default of p:64:64:64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197397 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 17:15:29 +00:00
Hao Liu
00a5490f87 [AArch64]Fix the pattern match failure for v1i8/v1i16/v1i32 types. 
Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them.
E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32:
     bitcast (load i32) to v1i32 -> load v1i32.
So this patch fixes such problems for load/dup instructions.
If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 02:51:28 +00:00
Chad Rosier
513a00db78 [AArch64] Simplify the Neon Scalar3Same patterns for floating-point reciprocal 
step, floating-point reciprocal square root step, floating-point absolute
difference, and integer/floating-point compare instructions.  Also, move the
scalar general arithmetic operation patterns closer to similar code.  No
functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197250 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-13 17:56:44 +00:00
Rafael Espindola
1cf81e6244 Simplify the datalayout string of ARM and AArch64. 
No functionality change.

Reviewed by Tim Northover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197172 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 17:43:37 +00:00
Chad Rosier
410ca67ab2 [AArch64] Removed unnecessary copy patterns with v1fx types. 
- Copy patterns with float/double types are enough.
- Fix typos in test case names that were using v1fx.
- There is no ACLE intrinsic that uses v1f32 type.  And there is no conflict of
  neon and non-neon ovelapped operations with this type, so there is no need to
  support operations with this type.
- Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for
  operations.

Patch by Ana Pazos!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197159 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 15:46:29 +00:00
Hao Liu
60a21f2238 [AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 07:36:26 +00:00
Chad Rosier
eb1bac0afa [AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64 
intrinsics to use f32 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 23:21:25 +00:00
Chad Rosier
87b627d88e [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics that 
use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197068 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:46 +00:00
Chad Rosier
73f468218f [AArch64] Refactor the NEON scalar floating-point reciprocal step and 
floating-point reciprocal square root step LLVM AArch64 intrinsics to
use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:43 +00:00
Chad Rosier
c3e5d72ba8 [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating- 
point reciprocal exponent, and floating-point reciprocal square root estimate
LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector
equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197066 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:40 +00:00
Kevin Qin
ec5ebdec47 [AArch64 NEON] Get instruction BSL matched to VSELECT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196998 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 02:33:50 +00:00
NAKAMURA Takumi
0d87d72fa7 Prune redundant dependencies in LLVMBuild.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196988 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 00:30:57 +00:00
Chad Rosier
b2282508d3 [AArch64] Refactor the NEON floating-point absolute difference LLVM AArch64 
intrinsic to use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196965 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:59 +00:00
Chad Rosier
2456ea5c92 [AArch64] Refactor the NEON signed/unsigned floating-point convert to fixed-point 
LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:56 +00:00
Chad Rosier
c000d11d5d [AArch64] Overload NEON signed/unsigned floating-point convert to fixed-point 
and fixed-point convert to floating-point LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196963 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:53 +00:00
Chad Rosier
d096a5c237 [AArch64] Overload NEON signed/unsigned integer convert to floating-point 
LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196962 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:50 +00:00
Chad Rosier
fafd264de4 [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics so 
that they use float/double rather than the vector equivalents when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196930 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 16:11:39 +00:00
Chad Rosier
72800f3a06 [AArch64] Refactor the Neon vector/scalar floating-point convert implementation. 
Specifically, reuse the ARM intrinsics when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196926 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 15:35:33 +00:00
Kevin Qin
cbb73d1b91 [AArch64 NEON] Replace fpimm with fpz32 for floating compare with zero. 
This is a small change to be strict. Just want get pattern safer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196889 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 06:51:07 +00:00
Kevin Qin
3171b8df48 [AArch64 NEON] Support poly128_t and implement relevant intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196887 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 06:48:35 +00:00
NAKAMURA Takumi
e1d55bb5d5 Add proper dependencies to LLVMBuild.txt in llvm/lib. 
I'll prune redundant deps in LLVMBuild.txt, later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196881 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 05:39:34 +00:00
NAKAMURA Takumi
e0c0c4bdf6 Whitespaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196880 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 05:39:12 +00:00
Chad Rosier
e02fa056d9 [AArch64] Refactor the NEON scalar reduce pairwise intrinsics, so that they use 
float/double rather than the vector equivalents when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196833 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:38 +00:00
Chad Rosier
97eda18693 [AArch64] Refactor NEON scalar reduce pairwise front-end codegen to remove 
unnecessary patterns in tablegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:34 +00:00
Chad Rosier
6c6344e6a9 [AArch64] Remove q and non-q intrinsic definitions in the NEON scalar reduce 
pairwise implementation, using an overloaded definition instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196831 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:31 +00:00
Ana Pazos
ddf4eb3d03 Fix pattern match for movi with 0D result 
Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196806 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 19:29:14 +00:00
Hao Liu
a339740cb8 [AArch64]Add missing pair intrinsics such as: 
int32_t vminv_s32(int32x2_t a)
which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196749 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 03:51:42 +00:00
Hao Liu
2f3f02f6f5 [AArch64]Pattern match failures for truncate store and extend load 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196748 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 03:34:08 +00:00
Ana Pazos
32cbcf2295 Implemented vget/vset_lane_f16 intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196533 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 21:07:49 +00:00
Jiangning Liu
4fd58529ab For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196456 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 02:12:01 +00:00
Kevin Qin
dd302615b1 [AArch64 Neon] Add ACLE intrinsic vceqz_f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196362 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-04 08:02:34 +00:00
Kevin Qin
c7f14e3d8c [AArch64 NEON] Add missing compare intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-04 07:53:28 +00:00
Hao Liu
1296bb3ba6 [AArch64]Add missing floating point convert, round and misc intrinsics. 
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196210 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 06:06:55 +00:00
Hao Liu
5025a48f68 AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions. 
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196208 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 05:58:30 +00:00
NAKAMURA Takumi
b26e6ecd8d Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196203 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 05:28:27 +00:00
Hao Liu
3d69ff4d07 AArch64: Add missing scalar pair intrinsics. 
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196198 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 03:39:47 +00:00
Jiangning Liu
bbc450c5cf Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196192 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 01:33:52 +00:00
Jiangning Liu
7f1f8d4146 Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196190 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 01:29:32 +00:00
Rafael Espindola
9472fd7403 Refactor the setting of PrivateGlobalPrefix. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196170 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 23:39:26 +00:00
Chad Rosier
d4809bb0e3 [AArch64] Implemented vcopy_lane patterns using scalar DUP instruction. 
Patch by Ana Pazos!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 21:05:16 +00:00