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39055b3a5c
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19001 Commits

Author SHA1 Message Date
Bill Wendling
39055b3a5c Update the comment. This feature is available only on Darwin at the moment. Though it's not Darwin-specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 20:15:15 +00:00
Jim Grosbach
43904299b0 Make assembly parser method names more consistent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 20:14:50 +00:00
Oscar Fuentes
7331ac47b9 Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 20:13:36 +00:00
Jim Grosbach
1610a70965 Tidy up formatting. 
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 20:06:30 +00:00
Jim Grosbach
1e93b24246 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135945 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 20:00:32 +00:00
Evan Cheng
b024572444 Missed a file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 19:55:33 +00:00
Evan Cheng
966aeb5788 Refactor PPC target to separate MC routines from Target routines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 19:53:23 +00:00
Evan Cheng
a87e40f16f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135939 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 19:33:48 +00:00
Evan Cheng
8c3fee5903 Refactor X86 target to separate MC code from Target code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 18:43:53 +00:00
Bill Wendling
c57e7dbfaf Changed disabled code into a flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 18:04:49 +00:00
Bill Wendling
091a864f06 Remove dead variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 18:01:27 +00:00
Bill Wendling
09b02c8ddd After we've modified the prolog to save volatile registers, generate the compact 
unwind encoding for that function. This simply crawls through the prolog looking
for machine instrs marked as "frame setup". It can calculate from these what the
compact unwind should look like.

This is currently disabled because of needed linker support. But initial tests
look good.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 18:00:28 +00:00
Roman Divacky
d5601cc810 Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135866 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-24 08:22:56 +00:00
NAKAMURA Takumi
883d99f70b ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 01:16:22 +00:00
Evan Cheng
a7cfc08ebe Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 00:45:41 +00:00
Evan Cheng
7f8dff6571 createXXXMCCodeGenInfo should be static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 00:01:04 +00:00
Evan Cheng
be74029f44 Sink ARM mc routines into MCTargetDesc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 00:00:19 +00:00
Jim Grosbach
4a5ffb399f ARM SSAT instruction 5-bit immediate handling. 
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 23:16:18 +00:00
Jim Grosbach
bf2845c0d8 ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:06:05 +00:00
Evan Cheng
e78085a3c0 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo, 
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:58:54 +00:00
Bruno Cardoso Lopes
dad38638e1 Fix PR10422 by adding the necessary AVX UCOMISD memory versions to 
load folding logic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:53:20 +00:00
Jim Grosbach
b544f68b70 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:18:21 +00:00
Jim Grosbach
b206daaec1 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:11:20 +00:00
Bruno Cardoso Lopes
8360b5fa81 Add v8f32->v8i32 bitcast. Fixes PR10440 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 19:51:02 +00:00
Rafael Espindola
23e31011fb Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64 
too. Patch by Jeff Muizelaar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:56:05 +00:00
Dan Gohman
6e5fda213f Fix x86's XALUO lowering to return its replacement values instead 
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:45:15 +00:00
Owen Anderson
e0a03143df Fix test failures caused by my so_reg refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135785 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:30:30 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:13:31 +00:00
Jim Grosbach
7931df3d74 Clean up a few more comments. 
These instruction definitions are for the assembler, too, not just the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:06:01 +00:00
Jim Grosbach
0fdf6ccf17 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:04:10 +00:00
Jim Grosbach
0632247818 Thumb assembly support for SETEND instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:52:23 +00:00
Jim Grosbach
53a89d6f38 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135777 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:46:13 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:44:50 +00:00
Jim Grosbach
6c1bb77992 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 16:59:04 +00:00
Chandler Carruth
48ac8e9be7 Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. 
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.

Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 08:16:53 +00:00
Benjamin Kramer
558cc5a914 GCC complains about the angle of this line. 
Remove the escaped newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 01:02:57 +00:00
Bruno Cardoso Lopes
c41e593509 Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't 
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:10 +00:00
Bruno Cardoso Lopes
6683efb4cd -Inspected a AVX code block added by someone in early Feb. This was never used 
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
74dad551d8 Add a DAGCombine for transforming 128->256 casts into a simple 
vxorps + vinsertf128 pair of instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:00 +00:00
Bruno Cardoso Lopes
d088834fb9 Introduce a new function to lower 256-bit vectors which are not 
direclty supported and should be promoted and handled by smaller
shuffles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:14:56 +00:00
Bruno Cardoso Lopes
589b897a31 Rename function to be more specific and be more strict about its usage 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135725 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:14:53 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:38:37 +00:00
Jim Grosbach
7c6e42e927 ARM Asm parser range checking for [0,31] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:26:25 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:37:43 +00:00
Jim Grosbach
43d3b31cda Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 21:26:05 +00:00
Nicolas Geoffray
a056d20167 Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 20:59:21 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:57:11 +00:00
Oscar Fuentes
45e11c7cc7 Fix CMake build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:10:57 +00:00
Owen Anderson
92a202213b Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 18:54:16 +00:00