Commit Graph

24 Commits

Author SHA1 Message Date
Colin LeMahieu
a0ce232a65 [Hexagon] Eliminating immediate condition set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 19:57:18 +00:00
Colin LeMahieu
70d77d1edc [Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 19:31:25 +00:00
Eric Christopher
40445ad91f Use the cached subtarget on the MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227885 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-02 22:40:56 +00:00
Colin LeMahieu
aa4172e1d8 [Hexagon] Dropping old combine instructions without encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-30 17:53:54 +00:00
Colin LeMahieu
526a14a344 [Hexagon] Updating doubleword shift usages to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 23:36:15 +00:00
Colin LeMahieu
015408c6b1 [Hexagon] Adding encoding information for sign extend word instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 16:43:06 +00:00
Colin LeMahieu
a3b01e5189 [Hexagon] Removing old def versions and replacing usages with versions that have encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223720 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 23:55:43 +00:00
Colin LeMahieu
5db47f1376 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:09:27 +00:00
Colin LeMahieu
609c7fa14e [Hexagon] Adding C2_mux instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 20:20:09 +00:00
Eric Christopher
6035518e3b Have MachineFunction cache a pointer to the subtarget to make lookups
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 02:39:49 +00:00
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:25:23 +00:00
Craig Topper
aab65f8023 [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207508 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 07:58:16 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:41:26 +00:00
Robert Wilhelm
3f4f420ab7 Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-28 13:42:22 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:58:00 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:22:51 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Pranav Bhandarkar
4c3d3ecdf8 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 16:01:40 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
Benjamin Kramer
120cfdf0e0 Remove unused cl::opt, make another opt static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151398 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 22:09:25 +00:00
Sirish Pande
ab7955b9ce Optimize redundant sign extends and negation of predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 18:52:27 +00:00
Eric Christopher
2a4bc1e703 Revert "Replacing HexagonOptimizeSZExtends with HexagonPeephole."
This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150605 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 18:34:25 +00:00
Sirish Pande
a997b3e51a Replacing HexagonOptimizeSZExtends with HexagonPeephole.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 18:31:35 +00:00