Commit Graph

9389 Commits

Author SHA1 Message Date
Benjamin Kramer
fc6434a73d Add a overload to CostTable which allows it to infer the size of the table.
Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType
in the TTI tables so they can be statically initialized, MVT's constructors
create bloated initialization code otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 19:33:32 +00:00
Michael J. Spencer
081a1941b5 [Object] Split the ELF interface into 3 parts.
* ELFTypes.h contains template magic for defining types based on endianess, size, and alignment.
* ELFFile.h defines the ELFFile class which provides low level ELF specific access.
* ELFObjectFile.h contains ELFObjectFile which uses ELFFile to implement the ObjectFile interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188022 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 22:27:13 +00:00
Jakub Staszak
91955e78e7 Use pop_back() instead of pop_back_val() when the returned value is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:48:46 +00:00
Jakub Staszak
72feef14f1 Fix the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:19:25 +00:00
Elena Demikhovsky
207600d2cf AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 12:34:55 +00:00
Craig Topper
b19982c42b Simplify code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187870 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 08:16:07 +00:00
Tim Northover
d113448c1d Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:

define i64 @test1(i64 %val) {
  %in = trunc i64 %val to i32
  tail call i32 @ret32(i32 returned %in)
  ret i64 %val
}

define i64 @test2(i64 %val) {
  tail call i32 @ret32(i32 returned undef)
  ret i32 42
}

should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.

For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
   than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
   call.

Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).

This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.

Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 09:12:35 +00:00
Craig Topper
5923547e2a Simplify vector lane handling math a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 07:23:12 +00:00
Craig Topper
57bc5a0b5b Simplify math a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:54:25 +00:00
NAKAMURA Takumi
8e1d64666f Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:38:37 +00:00
Craig Topper
aa0f420567 Replace EVT with MVT in isHorizontalBinOp as it is only called with legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:05:05 +00:00
Craig Topper
20b46b0733 Simplify code slightly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 04:12:40 +00:00
Aaron Ballman
2a37c7e9e6 Silencing an MSVC11 type conversion warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 13:47:03 +00:00
Elena Demikhovsky
13e6e9171f AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 08:52:21 +00:00
Benjamin Kramer
75311b7b4d X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }

before:
_test:
	ucomisd	%xmm0, %xmm1
	ja	LBB0_2
	movaps	%xmm3, %xmm2
LBB0_2:
	movaps	%xmm2, %xmm0

after:
_test:
	cmpltsd	%xmm1, %xmm0
	andpd	%xmm0, %xmm2
	andnpd	%xmm3, %xmm0
	orpd	%xmm2, %xmm0

Small speedup on Benchmarks/SmallPT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 12:05:16 +00:00
Elena Demikhovsky
f3e3417e65 AVX-512 set: added VEXTRACTPS instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 10:46:07 +00:00
Tim Northover
a54b66277e X86: correct tail return address calculation
Due to the weird and wondeful usual arithmetic conversions, some
calculations involving negative values were getting performed in
uint32_t and then promoted to int64_t, which is really not a good
idea.

Patch by Katsuhiro Ueno.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 09:35:57 +00:00
Bill Wendling
61fc8d670f Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:42:05 +00:00
Daniel Malea
44c8e346c7 Fixed the Intel-syntax X86 disassembler to respect the (existing) option for hexadecimal immediates, to match AT&T syntax. This also brings a new option for C-vs-MASM-style hex.
Patch by Richard Mitton
Reviewed: http://llvm-reviews.chandlerc.com/D1243



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187614 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:18:16 +00:00
Elena Demikhovsky
0780179d53 EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 13:34:06 +00:00
Elena Demikhovsky
093043ce11 Fixed assertion in Extract128BitVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:03:08 +00:00
Elena Demikhovsky
8395251c0a Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:35:14 +00:00
Craig Topper
418eb3df74 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:47:52 +00:00
Craig Topper
5bd1b815b3 Remove trailing whitespace and some tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:00:15 +00:00
Craig Topper
1a5c55e54d Fixed incorrect disassembly for MOV16o16a when using Intel syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 01:50:26 +00:00
Nico Rieck
944061c4e1 Proper va_arg/va_copy lowering on win64
Win64 uses CharPtrBuiltinVaList instead of X86_64ABIBuiltinVaList like
other 64-bit targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 13:07:06 +00:00
Elena Demikhovsky
c18f4efc5d Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:28:38 +00:00
Justin Holewinski
320185fa5f Add a target legalize hook for SplitVectorOperand (again)
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

Attempt to fix the buildbots by making the X86 test I just added platform independent

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 13:28:29 +00:00
Rafael Espindola
c735c1c2ae Revert "Add a target legalize hook for SplitVectorOperand"
This reverts commit 187198. It broke the bots.

The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 13:18:16 +00:00
Justin Holewinski
5a24ed951b Add a target legalize hook for SplitVectorOperand
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 12:46:39 +00:00
Craig Topper
35786c0505 Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 05:37:46 +00:00
Craig Topper
b3053c528a Take advantage of the register enums being in order to remove a couple static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 02:02:47 +00:00
Elena Demikhovsky
e3809eed34 I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 11:02:47 +00:00
Craig Topper
f63ef914b6 Split generated asm mnemonic matching table into a separate table for each asm variant.
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 07:33:14 +00:00
Craig Topper
f7beb2cc1f Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress them from being used by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 04:38:13 +00:00
Craig Topper
9564c1e9b8 Remove some errant space charcters in mnemonic strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186932 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:45:34 +00:00
Craig Topper
9b8b830f3f Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:50:47 +00:00
Craig Topper
5e4fa97a1d Revert r186907 to fix bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:29:37 +00:00
Craig Topper
36945d3d26 Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186907 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:21:36 +00:00
Craig Topper
1fd6e647bc Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix to their 32-bit forms.
This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 00:56:15 +00:00
Craig Topper
af1d08782b Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, %reg.
It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 00:15:19 +00:00
Craig Topper
19159c1f4c Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186897 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 00:03:33 +00:00
Kevin Enderby
877d123bdb Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 21:25:31 +00:00
Craig Topper
4e3170b63a Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 20:46:37 +00:00
Tim Northover
1abb7bc7e9 Revert "More Intel syntax alias fixes."
This reverts commit r186813, which broke the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 11:02:32 +00:00
Craig Topper
e64863c8b5 Fix typo. Change %cl to CL in Intel pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 10:07:26 +00:00
Craig Topper
1011c13f15 More Intel syntax alias fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 09:58:07 +00:00
Craig Topper
0ff6cf7f7e More Intel syntax alias fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 09:42:31 +00:00
Craig Topper
5e08ce288a Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 09:22:49 +00:00
Craig Topper
950bbfd43a Add Intel variants to aliases for some FP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 09:18:43 +00:00