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174 Commits

Author SHA1 Message Date
Craig Topper
2b5dc93948 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:32:42 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e43a0f8015 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:35:51 +00:00
Craig Topper
29d56f68c6 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 22:29:41 +00:00
Craig Topper
030ceadd69 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 05:09:27 +00:00
Craig Topper
d573aba8e1 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 19:12:10 +00:00
Craig Topper
163868fec5 Remove unused HasFROperands field from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198332 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:44:21 +00:00
Craig Topper
a7133ee752 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:20:48 +00:00
Craig Topper
d4e0bc4316 Remove unnecessary stirng comparison from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198325 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:41:40 +00:00
Craig Topper
e625100c6a Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:28:14 +00:00
Craig Topper
e61c70a085 Remove unused function argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198291 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 03:58:45 +00:00
Craig Topper
5cfd40ccd4 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 21:52:57 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:12:34 +00:00
Craig Topper
979b2cd2bc Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 14:22:37 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 17:21:44 +00:00
Craig Topper
e6d2dce7ab Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 19:16:48 +00:00
Craig Topper
d7109840cd Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 17:37:10 +00:00
Eric Christopher
75a8b23e10 [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-20 02:04:49 +00:00
Elena Demikhovsky
376a81d8ce AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
633f98bdfa AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-03 13:46:31 +00:00
Craig Topper
c6f7c99809 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 04:55:01 +00:00
Craig Topper
017d8a3e23 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 05:41:08 +00:00
Craig Topper
c429b5cca1 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 04:46:18 +00:00
Craig Topper
e799dbc4bd Remove another unnecessary filter from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 06:59:57 +00:00
Craig Topper
be5c1fd43f Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 04:26:52 +00:00
Craig Topper
5747f946ec More x86 disassembler filtering cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 06:12:53 +00:00
Craig Topper
10c7925d69 Remove some old filters from the x86 disassembler table builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 05:02:29 +00:00
Craig Topper
d55fed16a4 Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 06:30:39 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 07:19:47 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 04:28:06 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 05:17:48 +00:00
Elena Demikhovsky
1765e74c15 AVX-512: Added masked SHIFT commands, more encoding tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-22 12:18:28 +00:00
Craig Topper
d953bcd487 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187333 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-28 21:28:02 +00:00
Elena Demikhovsky
dc8a318f44 fixed compilation issue 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187325 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-28 08:45:12 +00:00
Elena Demikhovsky
c18f4efc5d Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-28 08:28:38 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 17:08:10 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-11 04:52:28 +00:00
Dave Zarzycki
9b3939983f x86 -- add the XTEST instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-25 18:59:43 +00:00
Kevin Enderby
12dccaed9c Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo
6c3daabc3e Added 0x0D to 2-byte opcode extension table for prefetch* variants 
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-12 00:19:12 +00:00
Chandler Carruth
4ffd89fa4d Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 10:37:14 +00:00
Michael Liao
be02a90de1 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-08 07:28:54 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 06:37:45 +00:00
Craig Topper
bf4043768c Add support for converting llvm.fma to fma4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 15:40:30 +00:00
Craig Topper
49d86c9eb9 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 06:48:11 +00:00
Craig Topper
95c929f45c Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 06:27:19 +00:00
Craig Topper
24fd0ddf31 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160949 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 05:39:34 +00:00
Craig Topper
50c5c8275e Simplify code that filtered certain instructions in two different ways. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160948 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 05:10:05 +00:00