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414e682bac
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1565 Commits

Author SHA1 Message Date
Jim Laskey
414e682bac Translate llvm target registers to dwarf register numbers properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 20:18:45 +00:00
Chris Lattner
749b758b2e unbreak the build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 16:52:45 +00:00
Evan Cheng
a0b3afbe14 Use pcmpeq to generate vector of all ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27167 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:00:16 +00:00
Nate Begeman
f15485a8d0 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 01:32:24 +00:00
Nate Begeman
c02e5a8668 Readme note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27152 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 19:19:27 +00:00
Evan Cheng
ffea91e522 Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 09:53:12 +00:00
Evan Cheng
6e16ee5634 Added missing (any_extend (load ...)) patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 09:45:48 +00:00
Evan Cheng
c60bd97b94 Build arbitrary vector with more than 2 distinct scalar elements with a 
series of unpack and interleave ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 09:37:23 +00:00
Chris Lattner
420736dc85 #include Intrinsics.h into all dag isels 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:47:10 +00:00
Evan Cheng
ecac9cb959 Added SSE cachebility ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:03:26 +00:00
Evan Cheng
cc4f047dca Instruction encoding bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27102 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:00:03 +00:00
Evan Cheng
7b1d34bc6c Added 128-bit packed integer subtraction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:33:37 +00:00
Evan Cheng
3246e06f84 Added CVTTPS2PI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27095 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:31:59 +00:00
Evan Cheng
7dda4052f5 Added CVTSS2SI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:00:18 +00:00
Evan Cheng
bc4832bc64 Support for scalar to vector with zero extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 23:15:12 +00:00
Evan Cheng
c653d48022 Added LDMXCSR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 22:28:37 +00:00
Chris Lattner
ac53eadc29 plug the intrinsics into the patterns for movmsk* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:49:18 +00:00
Jim Laskey
47622e3721 Add dwarf register numbering to register data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:15:58 +00:00
Evan Cheng
386031a06f Handle BUILD_VECTOR with all zero elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:29:27 +00:00
Chris Lattner
9d5da1d96c Gabor points out that we can't spell. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:12:19 +00:00
Evan Cheng
5217a5b58c All v2f64 shuffle cases can be handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27044 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 06:40:32 +00:00
Evan Cheng
2c0dbd01d2 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 02:58:06 +00:00
Evan Cheng
b20aaceb52 A new entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27039 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 02:57:03 +00:00
Evan Cheng
14aed5e66b Handle more shuffle cases with SHUFP* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 01:18:28 +00:00
Evan Cheng
8fc23cd0e9 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26997 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 20:26:04 +00:00
Jim Laskey
f1d78e8335 Add support to locate local variables in frames (early version.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:12:57 +00:00
Jim Laskey
99db0442f0 Change interface to DwarfWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26991 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:09:44 +00:00
Chris Lattner
29b4dd0c9c Fix the encodings of these new instructions, hopefully fixing the JIT 
failures from last night


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26981 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 16:13:50 +00:00
Evan Cheng
24dc1f5975 Following icc's lead: use movdqa to load / store 128-bit integer vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 07:44:07 +00:00
Chris Lattner
bc641b9d8b Eliminate IntrinsicLowering from TargetMachine. 
Make the CBE and V9 backends create their own, since they're the only ones that use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 05:43:16 +00:00
Evan Cheng
3b047f7bfa Add v4i32 <-> v4f32 bitconvert patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26969 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 02:36:37 +00:00
Evan Cheng
a971f6f967 Add 128-bit integer vector load and add (for testing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 01:57:24 +00:00
Nate Begeman
ce9448218a Add support for 8 bit immediates with 16/32 bit cmp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26966 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 01:29:48 +00:00
Evan Cheng
ca6e8eafd2 Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 22:07:06 +00:00
Evan Cheng
0cea6d2b9c SHUFP* are two address code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26959 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 20:08:18 +00:00
Evan Cheng
a88973f826 Some clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26957 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 19:22:18 +00:00
Evan Cheng
1bffadd7fb - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 19:16:21 +00:00
Evan Cheng
0188ecba85 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 18:59:22 +00:00
Evan Cheng
63d3300da1 - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 08:01:21 +00:00
Evan Cheng
2da953f77a Fix PSHUF* and SHUF* jit code emission problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 07:10:28 +00:00
Chris Lattner
6df1154644 fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 04:18:34 +00:00
Evan Cheng
b9df0ca67b Some splat and shuffle support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:53:00 +00:00
Evan Cheng
a9f2a717e9 Add a couple more pseudo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26939 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:52:03 +00:00
Evan Cheng
4a7da36546 Didn't mean to check this in. No MMX support yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26933 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:04:23 +00:00
Evan Cheng
48090aa814 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:01:21 +00:00
Chris Lattner
9b3bd467d0 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:51:05 +00:00
Evan Cheng
7ab54047e7 Combine 2 entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26921 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:18:26 +00:00
Evan Cheng
50a6d8c835 Add a note about x86 register coallescing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26920 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:12:57 +00:00
Evan Cheng
82521dd838 - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:09:35 +00:00
Evan Cheng
811ec1c92a x86 ISD::SCALAR_TO_VECTOR support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:33:35 +00:00