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14681 Commits

Author SHA1 Message Date
Daniel Dunbar
0481449a05 MC/X86: Extend suffix matching hack to match 'q' suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:54:20 +00:00
Daniel Dunbar
a5f1d57f65 MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can 
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:38:17 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 23:54:07 +00:00
Evan Cheng
9647f3d981 Avoid breaking vstd when reg_sequence is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 21:07:36 +00:00
Bill Wendling
f6d8481ada Simplify this logic of creating a default Features object. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103507 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:46:04 +00:00
Duncan Sands
16d8f8bd91 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:16:09 +00:00
Dan Gohman
99dca4fde7 Remove the "WantsWholeFile" concept, as it's no longer needed. CBE 
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 19:57:55 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 16:21:03 +00:00
Kalle Raiskila
2320a44b90 Make SPU backend not assert on jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 11:00:02 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Bill Wendling
3cbae239bb Don't create a StringRef with a NULL value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:33:39 +00:00
Evan Cheng
0ce537a9db Model some vst3 and vst4 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:19:40 +00:00
Bill Wendling
81043ee5dc The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a 
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 00:30:02 +00:00
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Kalle Raiskila
26c4cf4c6f Fix encoding of 'sf' and 'sfh' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 08:13:49 +00:00
Nathan Jeffords
bb59732d18 updated handling dllexport in X86AsmPrinter 
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 08:40:06 +00:00
Nathan Jeffords
071de920a0 made COFF target dllexport logic apply to all subtargets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 05:52:28 +00:00
Chris Lattner
b54b9ddaaf break coff symbol definition stuff out into proper MCStreamer callbacks, 
patch by Nathan Jeffords!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-08 19:54:22 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Devang Patel
ed66bf5125 Use overloaded operators instead of DIDescriptor::getNode() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:19:32 +00:00
Kalle Raiskila
021b5ef903 Testing svn access with a note added to documentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:06:28 +00:00
Chris Lattner
eb40a0fd98 switch MCSectionCOFF from a syntactic to semantic representation, 
patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 17:17:41 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Dan Gohman
0d881042c0 When rematerializing, use the debug location of the original 
instruction, rather than a location near where the new instruction
is being inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:28:10 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Daniel Dunbar
c26ae5ab7e MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. 
- This fixes "leal 0, %eax", for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 22:39:14 +00:00
Chris Lattner
e1611f26e3 fix rdar://7947167 - llvm-mc doesn't match movsq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:59:00 +00:00
Daniel Dunbar
a5d0b54ec1 MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since 
we don't currently support relaxing them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:34:01 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1 Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7 Cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267 storeRegToStackSlot has forgotten about QPR_8 register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Sean Callanan
be192dd1e9 Fixed a sign-extension bug in the X86 disassembler 
that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103128 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:47:27 +00:00
Evan Cheng
676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:15:40 +00:00
Dan Gohman
9f2cda73e4 No-ops emitted for scheduling don't correspond with anything in the 
user's source, so don't arbitrarily assign them a debug location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:58:01 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:28:36 +00:00
Evan Cheng
d2c2d1809f Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103103 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:27:57 +00:00
Eric Christopher
f4f06906b8 Revert 102941, we're going to do this via attr and can just 
hack the code to turn it off when debugging.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 07:35:59 +00:00
Eric Christopher
d2760d1cba Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 22:13:03 +00:00
Evan Cheng
94cc6d3a2b With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603 Do not pre-allocate for registers which form a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:38:12 +00:00
Chris Lattner
d4ac35b350 "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'." 
Patch by Kalle Raiskila!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 17:58:46 +00:00
Daniel Dunbar
e9f0fb4179 MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of 
instructions which have no direct register usage.

Darwin 'as' accepts:
  add $0, (%rax)
but rejects
  mov $0, (%rax)
for example.

Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 17:31:02 +00:00
Daniel Dunbar
c918d6043b MC/X86: Add "support" for matching ATT style mnemonic prefixes. 
- The idea is that when a match fails, we just try to match each of +'b', +'w',
   +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
   it. If all match, we assume it is width generic, and take the 'l' form.

 - This would be a horrible hack, if it weren't so simple. Therefore it is an
   elegant solution! Chris gets the credit for this particular elegant
   solution. :)

 - Next step to making this more robust is to have the X86 matcher generate the
   mnemonic prefix information. Ideally we would also compute up-front exactly
   which mnemonic to attempt to match, but this may require more custom code in
   the matcher than is really worth it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 16:12:42 +00:00
Gabor Greif
2f256f4561 fix operand indexes when outputting InvokeInsts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103003 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 09:23:54 +00:00
Kevin Enderby
a0161cd6f8 Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode 
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102991 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:42:46 +00:00
Jim Grosbach
6e62b4ef14 rdar://7937137 - dbg values not being handled in thumb1 version of 
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:11:37 +00:00
Dale Johannesen
08673d2950 Implement builtin_return_address(x) and builtin_frame_address(x) 
on PPC for x!=0.  7624113.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102972 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 22:59:34 +00:00
Kevin Enderby
9d0838fba8 Changed llvm-mc to use the same suffixes with floating point compare 
instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 21:31:40 +00:00
Kevin Enderby
eb612347f4 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from 
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 21:03:31 +00:00
Kevin Enderby
3c979b06c0 Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value 
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 20:45:05 +00:00
Eric Christopher
0b12348ddf Add an option, defaulting to off, to disable the sse domain crossing opts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102941 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 19:54:02 +00:00
Dan Gohman
3a2a4846a6 Add a README entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 14:31:00 +00:00
Duncan Sands
57b6e9eb6c Remove the -enable-sjlj-eh option, which doesn't do anything. 
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-02 15:36:26 +00:00
Chris Lattner
241d3fea7a fix some inconsistent line endings, patch by Jakub Staszak! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 17:36:49 +00:00
Anton Korobeynikov
1b17614a72 Do folding for indirect branches, where possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:28:21 +00:00
Anton Korobeynikov
69d5b48bc3 Implement indirect branches on MSP430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:04:32 +00:00
Anton Korobeynikov
650a8e49f9 Long branch target oparands are not pc-rel. 
This should fix PR6603.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102834 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:04:22 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Dan Gohman
acbfc157d2 Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 22:38:11 +00:00
Dan Gohman
3335a22a37 Make this code less confusing. Instead of reassigning BB, just operate 
on the original variables, so it's easier to see what is being done
to which blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 20:14:26 +00:00
Dan Gohman
71edb241a1 Remove the -disable-16bit command-line option, which is now obsolete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 18:30:26 +00:00
Evan Cheng
1361796dd0 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 01:12:32 +00:00
Dan Gohman
ffce6f1343 Don't leave Base.FrameIndex uninitialized, so that it doesn't 
print randomly in debug output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 23:30:41 +00:00
Dale Johannesen
8c5358c936 Make naked functions work on PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 19:32:19 +00:00
Devang Patel
67a444ca36 Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g. 
##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 18:52:10 +00:00
Evan Cheng
3f54c64a98 Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 05:08:22 +00:00
Mon P Wang
b9a01bcf48 Add support for assemblers that don't support periods in a name 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 04:00:56 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Kevin Enderby
9ac7282117 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the 
Operand size override prefix to be part of their records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 23:20:40 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Jakob Stoklund Olesen
7261fb2a6f Teach X86FloatingPoint that a register can be killed multiple times by the same 
instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 18:28:37 +00:00
Evan Cheng
2bce5f4b56 Enable i16 to i32 promotion by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 08:30:49 +00:00
Evan Cheng
39cfeecae5 Unbreak the build. Only form shld / shrd after legalization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 02:25:18 +00:00
Devang Patel
28ff35d030 Emit debug info for byval parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:39:28 +00:00
Evan Cheng
8b1190a540 Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:18:01 +00:00
Chris Lattner
a7b611c10d further simplify EmitAlignment by eliminating the 
ForcedAlignBits argument, tweaking the single client of it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:08:40 +00:00
Stuart Hastings
5a6a65be46 Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 00:35:10 +00:00
Devang Patel
a00adba6a7 Use MachineOperand::is* predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102472 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 22:24:37 +00:00
Evan Cheng
1c45acf510 Fix obvious typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 21:46:03 +00:00
Evan Cheng
b3716e3e28 SRA promotion is also not free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 19:48:31 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:37:21 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Dale Johannesen
efc3a6348a Add PPC AsmPrinter handling for target-specific form of 
DBG_VALUE, and a cautionary comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:05:01 +00:00
Evan Cheng
552f09a0d7 Promoting 16-bit cmp / test aren't free. Don't do it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 19:06:11 +00:00