Commit Graph

3321 Commits

Author SHA1 Message Date
Sasa Stankovic
10914379f6 [mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) and
%highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI
and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER
and VK_Mips_HIGHEST.

This change also deletes test file test/MC/Mips/higher_highest.ll and moves
its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s.
The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are
emitted in the .o file. Since it uses -force-mips-long-branch option, it was
created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and
R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch
started to directly calculate offsets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3230


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 10:37:45 +00:00
Kai Nacke
b96fc4a5ea [mips] Add more Octeon cnMips instructions
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:40:43 +00:00
Rafael Espindola
5d853bf42d Work around gold bug http://sourceware.org/PR16794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205416 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 12:15:20 +00:00
Kai Nacke
54c55edb0a [mips] Add Octeon cnMips instructions mtmX and mtpX
Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 18:35:26 +00:00
Daniel Sanders
f2452c4cec [mips] Extend ParseJumpTarget to support the full symbol expression syntax.
Summary:
This should fix the issues the D3222 caused in lld. Testcase is based on
the one that failed in the buildbot.

Depends on D3233

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3234

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205298 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:41:48 +00:00
Daniel Sanders
bd48d31b37 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:35:28 +00:00
David Blaikie
a07c1ab4e6 DebugInfo: Avoid creating unnecessary/empty line tables and remove the special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference
This moves one case of raw text checking down into the MCStreamer
interfaces in the form of a virtual function, even if we ultimately end
up consolidating on the one-or-many line tables issue one day, this is
nicer in the interim. This just generally streamlines a bunch of use
cases into a common code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 08:07:52 +00:00
David Blaikie
5b2de5dd3d DebugInfo: Emit relocation to debug_line section when emitting asm for asm
I don't think this is reachable by any frontend (why would you transform
asm to asm+debug info?) but it helps tidy up some of this code, avoid
the weird special case of "emit the first CU, store the label, then emit
the rest" in MCDwarfLineTable::Emit by instead having the
DWARF-for-assembly case use the same codepath as DwarfDebug.cpp, by
registering the label of the debug_line section, thus causing it to be
emitted. (with a special case in asm output to just emit the label since
asm output uses the .loc directives, etc, rather than the debug_loc
directly)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 07:35:52 +00:00
Rafael Espindola
c298307ae6 Don't relocate with sections if there might be a paired relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 19:00:23 +00:00
Daniel Sanders
1c056d8be9 Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests.
It's currently unable to parse 'sym + imm' without surrounding parenthesis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:51:43 +00:00
Rafael Espindola
524b776505 Now that this test is assembly, make the checks a bit stronger.
This will be used for a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205232 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:01:50 +00:00
Daniel Sanders
8f7dc89e21 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 17:43:46 +00:00
Daniel Sanders
e7c7ba0782 [mips] Implement missing relocations in the integrated assembler.
%got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised
by MipsAsmParser::getVariantKind().

To prevent future issues with missing entries in this StringSwitch, I've added
an assertion to the default case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:15:02 +00:00
Daniel Sanders
857d651ba4 [mips] Remove R_MIPS_GOT which isn't used and shares the same number as R_MIPS_GOT16
Unlike my previous commit, don't try to remove the corresponding VK_Mips_GOT yet
even though it shares the same assembly text since that is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:47:41 +00:00
Daniel Sanders
1df2ed27dd Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
There's a couple additional bits I missed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:34:36 +00:00
Daniel Sanders
1200528f17 [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:30:05 +00:00
NAKAMURA Takumi
6889086ba1 llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 13:30:02 +00:00
Daniel Sanders
5900e1db41 [mips] Added a full set of instruction test cases for all ISA's (but not ASE's).
Summary:
Where those ISA's are not currently supported, the test is run with the smallest
superset of that ISA.

Some instructions are valid but don't pass yet. These have been placed in the
valid-xfail.s's which will XPASS if _any_ instruction starts working.

The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 12:13:12 +00:00
Stepan Dyatkovskiy
b173d9ee35 PR18929:
According to ARM assembler language hash symbol is optional before immediates.
For example, see here for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 17:09:54 +00:00
NAKAMURA Takumi
2afefa27b3 llvm/test/MC/ELF/nocompression.s: Loosen an expression to match "llvm-mc.EXE".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 14:04:00 +00:00
Logan Chien
a68f166d60 llvm-mc: Fix build breakage caused by r205050.
When LLVM is not built with zlib, nocompression.s will test
for the error message.  But this test case will cause breakage
because the exit code is non-zero.  This commit fix this issue
by adding "not" to the command.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 15:10:22 +00:00
Stepan Dyatkovskiy
3fed2f133c Recommitted fix for PR18931, with extended tests set.
Issue subject: Crash using integrated assembler with immediate arithmetic

Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205094 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 13:12:40 +00:00
Tim Northover
7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
Rafael Espindola
224dbf4aec Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 06:26:49 +00:00
David Blaikie
1fc0d63775 Debug Compression: Avoid compression debug_frame for now
Turns out debug_frame does use multiple fragments, so it doesn't
compress correctly with the current approach. Disable compressing it for
now while I figure out what's the best solution for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 21:48:31 +00:00
David Blaikie
4a9c2585ab llvm-mc: error when -compress-debug-sections is requested and zlib is not linked
This is a bit of a stab in the dark, since I have zlib on my machine.
Just going to bounce it off the bots & see if it sticks.

Do we have some convention for negative REQUIRES: checks? Or do I just
need to add a feature like I've done here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205050 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 20:45:24 +00:00
Rafael Espindola
efd95481bd Convert one last llc -filetype=obj test.
Unfortunately this one fails deep inside the mips backend, so xfail it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205042 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:58:24 +00:00
Rafael Espindola
5811e45fb2 Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205040 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:41:33 +00:00
Rafael Espindola
24845fbabb Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205039 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:38:20 +00:00
Rafael Espindola
830ce8a06e Remove bogus test.
It was using "lc  -filetype=obj" just to pass the result to
"llvm-objdupm -disassemble" and then filecheck assembly.

The CHECK-NOT would never match anyway since it was missing $.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205036 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:26:05 +00:00
Rafael Espindola
e3b7d0228d Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:19:28 +00:00
Rafael Espindola
a53735bcf1 Map ELf flags back to more specific section kinds.
With that, convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:14:08 +00:00
Rafael Espindola
be560a3fb7 Parse .gpdword and convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:50:26 +00:00
Rafael Espindola
904658f8d4 convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:34:31 +00:00
Rafael Espindola
6b63578aab Convert "llc -filetype=obj" test into llvm-mc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:30:07 +00:00
David Blaikie
b91f51161f Only test compression when linked with zlib.
I'll implement error handling and a negative test in both llvm-mc and
Clang soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205016 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:04:53 +00:00
Christian Pirker
1f072c36d0 Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:35:30 +00:00
David Blaikie
0a0c4cc56f DebugInfo: Support for compressed debug info sections
1) When creating a .debug_* section and instead create a .zdebug_
   section.
2) When creating a fragment in a .zdebug_* section, make it a compressed
   fragment.
3) When computing the size of a compressed section, compress the data
   and use the size of the compressed data.
4) Emit the compressed bytes.

Also, check that only if a section has a compressed fragment, then that
is the only fragment in the section.

Assert-fail if the fragment's data is modified after it is compressed.

Initial review on llvm-commits by Eric Christopher and Rafael Espindola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204958 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 20:45:58 +00:00
Daniel Sanders
16dc6ed33f [mips] Attempting to use register $32 should be an error instead of an assertion.
Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 15:00:44 +00:00
Daniel Sanders
743cf74530 [mips] Add support for .cpsetup
Summary:
Patch by Robert N. M. Watson
His work was sponsored by: DARPA, AFRL

Small corrections by myself.

CC: theraven, matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204924 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 13:52:53 +00:00
Elena Demikhovsky
61785a0c3d AVX-512: Implemented masking for integer arithmetic & logic instructions.
By Robert Khasanov rob.khasanov@gmail.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 09:45:08 +00:00
Stepan Dyatkovskiy
fee5d23404 Rejected r204899 and r204900 due to remaining test failures on cmake-llvm-x86_64-linux buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:38:18 +00:00
Stepan Dyatkovskiy
a36286cb49 Fixed test for r204899 (pr18931 fix)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:20:26 +00:00
Stepan Dyatkovskiy
fccc6901d6 Fix for pr18931: Crash using integrated assembler with immediate arithmetic
Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:49:39 +00:00
Jiangning Liu
09b4588309 ARM: raise error message when complex SO expressions can't really be
solved as a constant at compilation time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:42:58 +00:00
Rafael Espindola
e459f72ee0 Correctly propagates st_size.
This also finally removes a bogus call to AliasedSymbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 00:28:24 +00:00
Kevin Enderby
9efa4ff901 Fix the ARM VST4 (single 4-element structure from one lane)
size 16 double-spaced registers instruction printing.

This:
	vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!

was being printed as:

	vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!

rdar://16435096


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 19:35:40 +00:00
Matheus Almeida
8e7aa4be58 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 16:09:43 +00:00
Matheus Almeida
75203b6d11 [mips] Add support to the '.dword' directive.
The '.dword' directive accepts a list of expressions and emits
them in 8-byte chunks in successive locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 15:44:18 +00:00
Matheus Almeida
5957d10b41 [mips] Add support to '.set mips64'.
The '.set mips64' directive enables the feature Mips:FeatureMips64
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204817 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 15:14:32 +00:00
Matheus Almeida
53ccc093bf [mips] Add support to '.set mips64r2'.
The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64r2 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 14:52:22 +00:00
Matheus Almeida
0de31d52d5 [mips] Add support for '.option pic2'.
The directive '.option pic2' enables PIC from assembly source.
At the moment none of the macros/directives check the PIC bit
but that's going to be fixed relatively soon. For example, the
expansion of macros like 'la' depend on the relocation model.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 13:40:29 +00:00
Daniel Sanders
23f0634162 [mips] Add tests for t0-t3 for N32/N64
These are aliases of t4-t7 and are provided for compatibility with both the
original ABI documentation (using t4-t7) and GNU As (using t0-t3)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:46:34 +00:00
Daniel Sanders
968ea7b82c [mips] The register names depend on the ABI being N32/N64 rather than the arch being mips64
Summary: Added test cases for O32 and N32 on MIPS64.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204796 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:39:07 +00:00
Daniel Sanders
95f4d65d4f [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 11:05:24 +00:00
Daniel Sanders
d431e0a20a [mips] Move the CHECK lines in mips*-register-names.s to make it more obvious which CHECK matches with which insn
This reveals a small mistake in mips-register-names.s ($sp is tested twice and
$s8 is not tested) which will be fixed in a follow-up commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 10:54:30 +00:00
Rafael Espindola
3008f80562 Correctly detect if a symbol uses a reserved section index or not.
The logic was incorrect for variables, causing them to end up in the wrong
section if the section had an index >= 0xff00.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 00:16:43 +00:00
Rafael Espindola
81c66bcc13 Create .symtab_shndxr only when needed.
We need .symtab_shndxr if and only if a symbol references a section with an
index >= 0xff00.

The old code was trying to figure out if the section was needed ahead of time,
making it a fairly dependent on the code actually writing the table. It was
also somewhat conservative and would create the section in cases where it was
not needed.

If I remember correctly, the old structure was there so that the sections were
created in the same order gas creates them. That was valuable when MC's support
for ELF was new and we tested with elf-dump.py.

This patch refactors the symbol table creation to another class and makes it
obvious that .symtab_shndxr is really only created when we are about to output
a reference to a section index >= 0xff00.

While here, also improve the tests to use macros. One file is one section
short of needing .symtab_shndxr, the second one has just the right number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204769 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 23:44:25 +00:00
Daniel Sanders
3527e5fcb3 [mips] '.set at=$0' should be equivalent to '.set noat'
Differential Revision: http://llvm-reviews.chandlerc.com/D3171

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204714 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 13:01:06 +00:00
Daniel Sanders
c7e1663c24 [mips] Correct testcase for .set at=$reg and emit the new warnings for numeric registers too.
Summary:
Remove the XFAIL added in my previous commit and correct the test such that
it correctly tests the expansion of the assembler temporary.

Also added a test to check that $at is always $1 when written by the
user.

Corrected the new assembler temporary warnings so that they are emitted for
numeric registers too.

Differential Revision: http://llvm-reviews.chandlerc.com/D3169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 11:16:03 +00:00
Daniel Sanders
c141b331b9 [mips] Fix assembler temporary expansion and add associated warnings about the use of $at.
Summary:
The assembler temporary is normally $at ($1) but can be reassigned using
'.set at=$reg'. Regardless of which register is nominated as the assembler
temporary, $at remains $1 when written by the user.

Adds warnings under the following conditions:
* The register nominated as the assembler temporary is used by the user.
* '.set noat' is in effect and $at is used by the user.
Both of these only work for named registers. I have a follow up commit that makes it work for numeric registers as well.

XFAIL set-at-directive.s since it incorrectly tests that $at is redefined by
'.set at=$reg'. Testcases will follow in a separate commit.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 10:57:07 +00:00
Kevin Enderby
4a88cd08da Fix crashes when assembler directives are used that are not
for Mach-O object files by generating an error instead.

rdar://16335232


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204687 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 00:05:50 +00:00
Ulrich Weigand
47eac58333 [PowerPC] Generate little-endian object files
As a first step towards real little-endian code generation, this patch
changes the PowerPC MC layer to actually generate little-endian object
files.  This involves passing the little-endian flag through the various
layers, including down to createELFObjectWriter so we actually get basic
little-endian ELF objects, emitting instructions in little-endian order,
and handling fixups and relocations as appropriate for little-endian.

The bulk of the patch is to update most test cases in test/MC/PowerPC
to verify both big- and little-endian encodings.  (The only test cases
*not* updated are those that create actual big-endian ABI code, like
the TLS tests.)

Note that while the object files are now little-endian, the generated
code itself is not yet updated, in particular, it still does not adhere
to the ELFv2 ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:16:09 +00:00
Daniel Sanders
8ce101ed10 [mips] Add error message when trying to use $at in '.set noat' mode.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:48:01 +00:00
Daniel Sanders
75002071fd [mips] Add regression tests for parenthetic expressions in MIPS assembly.
Summary:
These expressions already worked but weren't tested.

Patch by Robert N. M. Watson and David Chisnall (it was originally two patches)
Their work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 15:42:21 +00:00
Daniel Sanders
eaae583095 [mips] Allow dsubu to take an immediate as an alias for dsubiu.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3155

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 15:38:00 +00:00
Daniel Sanders
67db74e02c [mips] Implement shorthand add / sub forms for MIPS.
Summary:
- If only two registers are passed to a three-register operation, then the
  first argument is both source and destination register.

- If a non-register is passed as the last argument, generate the immediate
  version of the instruction.

Also mark DADD commutative and add scheduling information (to the generic
scheduler), and implement DSUB.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 14:05:39 +00:00
Rafael Espindola
2236f9348d Teach llvm-readobj to print human friendly description of reserved sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 05:00:34 +00:00
Rafael Espindola
0259b8e14f Add back tests that were reverted in r204203.
They pass again with the fix in r204581.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 03:48:15 +00:00
Rafael Espindola
0bce3343cc Propagate section from base to derived symbol.
We were already propagating the section in

a = b

With this patch we also propagate it for

a = b + 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 03:43:21 +00:00
Rafael Espindola
4ff2dadebe Propagate types from symbol to aliases.
This is similar, but not identical to what gas does. The logic in MC is to just
compute the symbol table after parsing the entire file. GAS is mixed, given

.type b, @object
a = b
b:
.type b, @function

It will propagate the change and make 'a' a function. Given

.type b, @object
b:
a = b
.type b, @function

the type of 'a' is still object.

Since we do the computation in the end, we produce a function in both cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 03:33:20 +00:00
Saleem Abdulrasool
7afe0000f6 ARM IAS: properly handle function entries in .thumb
When a label is parsed, check if there is type information available for the
label.  If so, check if the symbol is a function.  If the symbol is a function
and we are in thumb mode and no explicit thumb_func has been emitted, adjust the
symbol data to indicate that the function definition is a thumb function.

The application of this inferencing is improved value handling in the object
file (the required thumb bit is set on symbols which are thumb functions).  It
also helps improve compatibility with binutils.

The one complication that arises from this handling is the MCAsmStreamer.  The
default implementation of getOrCreateSymbolData in MCStreamer does not support
tracking the symbol data.  In order to support the semantics of thumb functions,
track symbol data in assembly streamer.  Although O(n) in number of labels in
the TU, this is already done in various other streamers and as such the memory
overhead is not a practical concern in this scenario.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-22 19:26:18 +00:00
Rafael Espindola
a60f719c8d Fix the value computation in
sym_a:
sym_d = sym_a + 1

This is the smallest fix I was able to extract from what got reverted in
r204203.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 22:00:29 +00:00
Rafael Espindola
3f687d350c Move codegen test over to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204490 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 17:55:34 +00:00
Rafael Espindola
6c22b041da Split out the MC part of this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204481 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 17:16:11 +00:00
Richard Sandiford
6b6889d87b [SystemZ] Add support for z196 float<->unsigned conversions
These complement the older float<->signed instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 10:56:30 +00:00
Jiangning Liu
705e53e2aa This reverts commit r203762, "ARM: support emission of complex SO expressions".
The commit r203762 introduced silent failure for complext SO expression, and it's even worse than compiler crash.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 02:51:01 +00:00
Rafael Espindola
5b460ed4cd Convert a CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 00:55:42 +00:00
Rafael Espindola
aeb12e91d1 Convert another CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 23:35:00 +00:00
Greg Fitzgerald
aff0ab4e7c llvm-objdump output hex to match binutils' objdump
Patch by Ted Woodward

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204409 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 22:55:15 +00:00
Rafael Espindola
f59d05cf35 Convert CodeGen test into a more specific MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204406 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 22:05:59 +00:00
Kai Nacke
ebf9f0c6cb [MIPS] Add cpu octeon and some instructions
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 11:51:58 +00:00
Zoran Jovanovic
37fb9b9591 Provide an operand for microMIPS wait instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204329 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 10:41:37 +00:00
Zoran Jovanovic
3ac3e7451b Implementation of microMIPS 16-bit instructions MOVE and JALR.
Differential Revision: http://llvm-reviews.chandlerc.com/D3112


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204325 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 10:18:24 +00:00
Zoran Jovanovic
b71fd20f2d Mark alias symbols as microMIPS if necessary. Differential Revision: http://llvm-reviews.chandlerc.com/D3080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 09:44:49 +00:00
Craig Topper
6ee83c07a0 Test case for r204305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204316 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 06:45:10 +00:00
Saleem Abdulrasool
9320b807aa Reapply 'ARM IAS: support .thumb_set'
Re-apply the change after it was reverted to do conflicts due to another change
being reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204306 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 06:05:33 +00:00
Rafael Espindola
0a70f9b3b9 Look through variables when computing relocations.
Given

bar = foo + 4
	.long bar

MC would eat the 4. GNU as includes it in the relocation. The rule seems to be
that a variable that defines a symbol is used in the relocation and one that
does not define a symbol is evaluated and the result included in the relocation.

Fixing this unfortunately required some other changes:

* Since the variable is now evaluated, it would prevent the ELF writer from
  noticing the weakref marker the elf streamer uses. This patch then replaces
  that with a VariantKind in MCSymbolRefExpr.

* Using VariantKind then requires us to look past other VariantKind to see

	.weakref	bar,foo
	call	bar@PLT

  doing this also fixes

	zed = foo +2
	call zed@PLT

  so that is a good thing.

* Looking past VariantKind means that the relocation selection has to use
  the fixup instead of the target.

This is a reboot of the previous fixes for MC. I will watch the sanitizer
buildbot and wait for a build before adding back the previous fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204294 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 02:12:01 +00:00
Matheus Almeida
947fa5b7b7 [mips] Making sure that a '.set noreorder' directive is correctly parsed
and emitted and that no NOPs are emitted in a 'noreorder section'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204250 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 16:20:19 +00:00
Rafael Espindola
94ec09ae32 Make the test harder by using a non-zero offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 00:26:58 +00:00
Rafael Espindola
025e94d7dc Revert "Add back r203962, r204028 and r204059."
This reverts commit r204178.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 00:13:43 +00:00
NAKAMURA Takumi
2c4507e850 Move yet another test that requires ARM to an ARM test directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204198 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 23:12:09 +00:00
Jim Grosbach
ec8a8564f8 Move tests that require ARM to an ARM test directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 22:43:59 +00:00
Jim Grosbach
d55fc3f151 Darwin: Add assembler directives to create version-min load commands.
Allow object files to be tagged with a version-min load command for iOS
or MacOSX.

Teach macho-dump to understand the version-min load commands for
testcases.

rdar://11337778

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204190 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 22:09:05 +00:00
Rafael Espindola
4af106a677 Add back r203962, r204028 and r204059.
This reverts commit r204137.

This includes a fix for handling aliases of aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204178 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 20:40:38 +00:00
Alexander Kornienko
8a99824c5a Revert r203962 and two revisions depending on it: r204028 and r204059.
The revision I'm reverting breaks handling of transitive aliases. This blocks us
and breaks sanitizer bootstrap:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/2651
(and checked locally by Alexey).

This revision is the result of:

  svn merge -r204059:204058 -r204028:204027 -r203962:203961 .

+ the regression test added to test/MC/ELF/alias.s

Another way to reproduce the regression with clang:
  $ cat q.c
  void a1();
  void a2() __attribute__((alias("a1")));
  void a3() __attribute__((alias("a2")));
  void a1() {}

  $ ~/work/llvm-build/bin/clang-3.5-good -c q.c && mv q.o good.o && \
      ~/work/llvm-build/bin/clang-3.5-bad -c q.c && mv q.o bad.o && \
      objdump -t good.o bad.o

    good.o:     file format elf64-x86-64

    SYMBOL TABLE:
    0000000000000000 l    df *ABS*  0000000000000000 q.c
    0000000000000000 l    d  .text  0000000000000000 .text
    0000000000000000 l    d  .data  0000000000000000 .data
    0000000000000000 l    d  .bss   0000000000000000 .bss
    0000000000000000 l    d  .comment       0000000000000000 .comment
    0000000000000000 l    d  .note.GNU-stack        0000000000000000 .note.GNU-stack
    0000000000000000 l    d  .eh_frame      0000000000000000 .eh_frame
    0000000000000000 g     F .text  0000000000000006 a1
    0000000000000000 g     F .text  0000000000000006 a2
    0000000000000000 g     F .text  0000000000000006 a3



    bad.o:     file format elf64-x86-64

    SYMBOL TABLE:
    0000000000000000 l    df *ABS*  0000000000000000 q.c
    0000000000000000 l    d  .text  0000000000000000 .text
    0000000000000000 l    d  .data  0000000000000000 .data
    0000000000000000 l    d  .bss   0000000000000000 .bss
    0000000000000000 l    d  .comment       0000000000000000 .comment
    0000000000000000 l    d  .note.GNU-stack        0000000000000000 .note.GNU-stack
    0000000000000000 l    d  .eh_frame      0000000000000000 .eh_frame
    0000000000000000 g     F .text  0000000000000006 a1
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    0000000000000000 g       .text  0000000000000000 a3




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204137 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 10:36:11 +00:00
Saleem Abdulrasool
5b5e5abd20 ARM IAS: support .thumb_set
This performs the equivalent of a .set directive in that it creates a symbol
which is an alias for another symbol or value which may possibly be yet
undefined.  This directive also has the added property in that it marks the
aliased symbol as being a thumb function entry point, in the same way that the
.thumb_func directive does.

The current implementation fails one test due to an unrelated issue.  Functions
within .thumb sections are not marked as thumb_func.  The result is that
the aliasee function is not valued correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 17:13:54 +00:00
NAKAMURA Takumi
6e3aceffd3 llvm/test/MC/MachO/gen-dwarf-cpp.s: Relax an expression to match DOS pat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204030 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 05:31:54 +00:00
Rafael Espindola
9fdf9d2a1e Consider the base pointer for setting the symbol type.
This is really a consistency fix. Since given

a = b

we propagate the information, we should propagate it too given

a = b + (1 - 1)

Fixes pr19145.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 04:29:51 +00:00
David Blaikie
fd69cf9ba4 DebugInfo: Improve reuse of file table entries in asm debug info
The previous deduping strategy was woefully inadequate - it only
considered the most recent file used and avoided emitting a duplicate in
that case - never considering the a/b/a scenario.

It was also lacking when it came to directory paths as the previous
filename would never match the current if the filename had been split
into file and directory components.

This change builds caching functionality into the line table at the
lowest level in an optional form (a file number of 0 indicates that one
should be chosen and returned) and will eventually be reused by the
normal source level debugging DWARF emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 01:52:11 +00:00