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Author SHA1 Message Date
Craig Topper
49d86c9eb9 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 06:48:11 +00:00
Craig Topper
95c929f45c Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 06:27:19 +00:00
Craig Topper
24fd0ddf31 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160949 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 05:39:34 +00:00
Craig Topper
50c5c8275e Simplify code that filtered certain instructions in two different ways. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160948 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 05:10:05 +00:00
Craig Topper
87a9ece154 Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160946 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 04:53:00 +00:00
Craig Topper
e6c97ffb0d Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160945 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 04:48:12 +00:00
Craig Topper
706698e0b7 Give VCVTTPD2DQ priority over CVTTPD2DQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160942 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:20:32 +00:00
Craig Topper
80e13a5506 Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:14:02 +00:00
Craig Topper
3ff91c3ac6 Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160939 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 01:38:57 +00:00
Craig Topper
19006bdee1 Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 23:26:34 +00:00
Craig Topper
26a79b7b94 Move more SSE/AVX convert instruction patterns into their definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 22:30:06 +00:00
Benjamin Kramer
a77b95a316 APInt: Simplify code. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 12:33:29 +00:00
Manman Ren
e8b4a4a9d1 Revert r160920 and r160919 due to dragonegg and clang selfhost failure 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 02:44:09 +00:00
Nick Lewycky
d64cb165d7 Add testcases for GlobalOpt changes in r160693 and r160757. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160925 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 01:15:37 +00:00
Craig Topper
7fe1b96ef0 Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:59:19 +00:00
Craig Topper
eb6d794834 Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160921 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:36:39 +00:00
Manman Ren
14148c41d9 X86 Peephole: fold loads to the source register operand if possible. 
Trying to fix the bot by specifying a triple in the failing testing cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160920 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 17:51:24 +00:00
Manman Ren
0eb3edea9c X86 Peephole: fold loads to the source register operand if possible. 
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 16:48:01 +00:00
Craig Topper
cdfbcdeeed Make CVTSS2SI instruction definition consistent with CVTSD2SI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 08:28:23 +00:00
Craig Topper
e96d11c833 Fix up memory load types for SSE scalar convert intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160913 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 07:59:59 +00:00
Manman Ren
43d9ab1812 X86 Peephole: fix PR13475 in optimizeCompare. 
It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160912 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 03:15:46 +00:00
Andrew Trick
4b72ada1f4 Reenable a basic SSA DAG builder optimization. 
Jakob fixed ProcessImplicifDefs in r159149.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160910 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 01:48:15 +00:00
Jakob Stoklund Olesen
08f6ef6a78 Add more debug output to MachineTraceMetrics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160905 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 23:58:38 +00:00
Jakob Stoklund Olesen
0271a5fa29 Keep track of the head and tail of the trace through each block. 
This makes it possible to quickly detect blocks that are outside the
trace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160904 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 23:58:36 +00:00
Eric Christopher
c23b933d5f Add a DW_AT_high_pc for CUs that are a single address range. Update 
all tests accordingly.

Fixes PR13351.

Patch by shinichiro hamaji!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160899 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 22:00:05 +00:00
Jakob Stoklund Olesen
c16bf79303 Also compute register mask lists under -new-live-intervals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 21:56:39 +00:00
Chad Rosier
21edb397b2 Typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160897 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 21:41:59 +00:00
Evan Cheng
9c777a4844 Teach CodeGenPrep to look past bitcast when it's duplicating return instruction 
into predecessor blocks to enable tail call optimization.

rdar://11958338


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160894 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 21:21:26 +00:00
Jakob Stoklund Olesen
b18d779b35 Eliminate the IS_PHI_DEF flag and VNInfo::setIsPHIDef(). 
A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160893 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 21:11:14 +00:00
Jakob Stoklund Olesen
3dfa38a5bf Add a -new-live-intervals experimental option. 
This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160892 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 20:58:46 +00:00
Andrew Kaylor
d83a547d67 Fixing problems with X86_64_32 relocations and making the assertions more readable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160889 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 20:30:12 +00:00
Jakob Stoklund Olesen
72e7dbf88b Add <imp-def> of super-register when lowering SUBREG_TO_REG. 
Patch by Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160888 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 20:19:49 +00:00
Benjamin Kramer
e82fafe9e2 SmallVector: Crank up verbosity of asserts per Chandler's request. 
Also add assertions to validate the iterator in the insert method overloads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160882 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 19:05:58 +00:00
Chad Rosier
85aa390713 The TimePassesIsEnabled has since moved to PassManager.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 19:03:02 +00:00
Andrew Kaylor
e2e73bd044 Test commit, clean up comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160880 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 18:39:47 +00:00
Nuno Lopes
e982de7be9 fix PR13390: do not loop forever with self-referencing self instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160876 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 18:21:15 +00:00
Nuno Lopes
75564e3514 fix infinite loop in instcombine in the presence of a (malformed) self-referencing select inst. 
This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160874 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 18:03:57 +00:00
Andrew Kaylor
2e319870f1 Test commit, clean up comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160873 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 17:52:42 +00:00
Jakob Stoklund Olesen
46c0dc7858 Give MCRegisterInfo an implementation file. 
Move some functions from MCRegisterInfo.h that don't need to be inline.

This shrinks llc by 8K.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160865 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 16:25:20 +00:00
Benjamin Kramer
df7c5d4137 SmallVector::erase: Assert that iterators are actually inside the vector. 
The rationale here is that it's hard to write loops containing vector erases and
it only shows up if the vector contains non-trivial objects leading to crashes
when forming them out of garbage memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160854 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 09:10:25 +00:00
Craig Topper
f553587a4f Clean up includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160852 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 06:44:02 +00:00
Jakob Stoklund Olesen
0371cd8b1c Eliminate the large XXXSubRegTable constant arrays. 
These tables were indexed by [register][subreg index] which made them,
very large and sparse.

Replace them with lists of sub-register indexes that match the existing
lists of sub-registers. MCRI::getSubReg() becomes a very short linear
search, like getSubRegIndex() already was.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160843 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-27 00:10:51 +00:00
Jakob Stoklund Olesen
2ca6b3c374 Remove support for 'CompositeIndices' and sub-register cycles. 
Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone,
there is no longer a need for the CompositeIndices construct in .td
files. Sub-register index composition can be specified on the
SubRegIndex itself using the ComposedOf field.

Also enforce unique names for sub-registers in TableGen. The same
sub-register cannot be available with multiple sub-register indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160842 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:39:50 +00:00
Akira Hatanaka
480eeb5431 Pass the correct call frame size to callseq_start node. This is needed to 
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:27:01 +00:00
Pete Cooper
7971de4178 Simplify demanded bits of select sources where the condition is a constant vector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160835 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:10:24 +00:00
Jakob Stoklund Olesen
3ba90d9c0e Remove the X86 sub_ss and sub_sd sub-register indexes completely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160833 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:07:20 +00:00
Jakob Stoklund Olesen
f992348ffb Remove the last mentions of sub_ss and sub_sd from patterns. 
I'll remove these two sub-register indexes shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160831 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:03:08 +00:00
Jakob Stoklund Olesen
4db2dbf921 Eliminate sub_ss, sub_sd from broadcast patterns. 
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but
copyPhysReg does the right thing with it. (The old pattern would
eventually produce the same cross-class copy).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160830 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:59:06 +00:00
Pete Cooper
1121c786fc Teach SimplifyDemandedBits how to look through fpext and fptrunc to simplify their operand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160823 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:37:04 +00:00
Jakob Stoklund Olesen
79ad138a33 Eliminate more sub_ss / sub_sd patterns. 
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns,
simplifying the emitted code a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160820 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:30:18 +00:00