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49eaf76c53
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17855 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
49eaf76c53 Fix an old copy-n-paste 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:20:24 +00:00
Devang Patel
53dc40a45f Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:11:05 +00:00
Bruno Cardoso Lopes
5d6fb5db90 Expands FCOS and FSIN nodes when type is f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 18:54:14 +00:00
Bruno Cardoso Lopes
911a992c33 Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
81092dc20a Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 17:51:39 +00:00
Kalle Raiskila
31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
7f5de8b4c6 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 12:00:11 +00:00
Eli Friedman
ac39bd534b PR9377: Handle x86 str with register operand in a way consistent with gas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 00:10:17 +00:00
Bob Wilson
58f04fd22a PR8053: Fix encoding of S bit in some ARM instructions. 
Patch by Zonr Chang!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 23:07:15 +00:00
Richard Osborne
022708f221 Optimize fprintf -> iprintf if there are no floating point arguments 
and siprintf is available on the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 14:20:22 +00:00
Justin Holewinski
43b4e23bac PTX: Fix Emacs renaming a symbol 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 14:09:40 +00:00
Richard Osborne
419454ad37 Optimize sprintf -> siprintf if there are no floating point arguments 
and siprintf is available on the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 14:09:28 +00:00
Justin Holewinski
12785e87e8 PTX: Fix a couple of lint violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 13:34:29 +00:00
Richard Osborne
3649824bec Optimize printf -> iprintf if there are no floating point arguments 
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 13:17:51 +00:00
Tilmann Scheller
49d7999b89 Use X86_thiscall calling convention for Win64 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:49:07 +00:00
Bob Wilson
acc9e7315c Add a readme entry for the redundant movw issue for pr9370. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 06:39:09 +00:00
Bob Wilson
181d3fe727 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 01:41:01 +00:00
Kevin Enderby
d39647d913 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:08:33 +00:00
Renato Golin
e89a05337a Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 21:20:09 +00:00
Tilmann Scheller
f1cc70ca93 Add Win64 thiscall calling convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 19:29:22 +00:00
David Greene
a20244d1ba [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 17:23:43 +00:00
Che-Liang Chiou
31c488c8bd ptx: fix lint and compiler warnings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126838 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 07:58:46 +00:00
Che-Liang Chiou
f48817cbf9 Add 64-bit addressing to PTX backend 
- Add '64bit' sub-target option.
- Select 32-bit/64-bit loads/stores based on '64bit' option.
- Fix function parameter order.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 07:36:48 +00:00
Che-Liang Chiou
fd8978b021 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:20:28 +00:00
Duncan Sands
c92cb649e3 Add datalayout information for the IEEE quad precision fp128 type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 20:56:50 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Chris Lattner
d3e768ecab add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 00:24:51 +00:00
Renato Golin
728ff0db78 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 22:04:27 +00:00
Kevin Enderby
4da434cd40 Add missing whitespace in the formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 21:45:12 +00:00
Chris Lattner
99825b4455 fix a signed comparison warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 20:50:35 +00:00
David Greene
c4db4e5105 [AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit 
and 256-bit forms.  Because the number of elements in a vector
      does not determine the vector type (4 elements could be v4f32 or
      v4f64), pass the full type of the vector to decode routines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 19:06:56 +00:00
Kevin Enderby
d436d5b1c9 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:46:31 +00:00
Evan Cheng
c24ab5c654 Fix a typo which cause dag combine crash. rdar://9059537. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:45:27 +00:00
Stuart Hastings
f222e595c0 Support for byval parameters on ARM. Will be enabled by a forthcoming 
patch to the front-end.  Radar 7662569.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 17:17:53 +00:00
Kalle Raiskila
2d25d247bd Add branch hinting for SPU. 
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 14:08:24 +00:00
Che-Liang Chiou
f71720231f Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 06:34:09 +00:00
Benjamin Kramer
9e9bb0871d Silence enum conversion warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 18:13:53 +00:00
NAKAMURA Takumi
419f232783 Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:47:19 +00:00
Benjamin Kramer
7466678003 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-26 22:48:07 +00:00
Owen Anderson
95771afbfd Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 21:41:48 +00:00
Cameron Zwarich
f754f50805 Roll out r126425 and r126450 to see if it fixes the failures on the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 16:30:32 +00:00
Bob Wilson
da52506792 Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 06:42:42 +00:00
Evan Cheng
9831f2d585 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 01:29:29 +00:00
Evan Cheng
acca09bd64 Each prologue may have multiple vpush instructions to store callee-saved 
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 00:24:46 +00:00
Chris Lattner
12d18a07a0 remove command line option debugging hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 21:53:03 +00:00
Devang Patel
f410608271 Enable DebugInfo support for COFF object files. 
Patch by Nathan Jeffords!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 21:04:00 +00:00
Richard Osborne
21d7eb3f3b Add XCore intrinsic for eeu instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 13:39:18 +00:00
Evan Cheng
7558e2e415 Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 02:36:52 +00:00
Richard Osborne
d04b4937d1 Add XCore intrinsic for clre instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:35:59 +00:00