Evan Cheng
d594881a28
- Emit subsections_via_symbols for Darwin.
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- Conditionalize Dwarf debugging output (Darwin only for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26582 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-07 02:23:26 +00:00
Evan Cheng
3c992d291b
Enable Dwarf debugging info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26581 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-07 02:02:57 +00:00
Chris Lattner
bbf1c72d51
implement TII::insertNoop
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 23:49:55 +00:00
Chris Lattner
5b0fe7d91d
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26549 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 20:00:08 +00:00
Chris Lattner
9601a86a64
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
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implement copysign as a native op if they have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 05:08:37 +00:00
Chris Lattner
a4929df2da
add a note for something evan noticed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26539 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 01:15:18 +00:00
Chris Lattner
9f17be690e
Implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26536 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 23:33:44 +00:00
Chris Lattner
ad01993194
Add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26523 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 08:44:51 +00:00
Evan Cheng
f42f516984
Add an entry
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26520 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 07:49:50 +00:00
Evan Cheng
62bec2ca4c
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
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rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26517 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 02:48:56 +00:00
Chris Lattner
b27b69f283
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26513 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 01:19:34 +00:00
Evan Cheng
8df346b4e8
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26512 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 01:12:00 +00:00
Chris Lattner
a8309ae1cb
Split the valuetypes out of Target.td into ValueTypes.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26490 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 01:55:26 +00:00
Chris Lattner
41edaa0529
remove the read/write port/io intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 00:19:58 +00:00
Chris Lattner
89188a1096
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26472 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-02 22:34:38 +00:00
Chris Lattner
0f6ab6ff97
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 07:14:48 +00:00
Chris Lattner
00d18f0879
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 06:36:20 +00:00
Chris Lattner
5126984b1d
Compile this:
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void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 05:50:56 +00:00
Chris Lattner
8c13d0a573
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:57:39 +00:00
Evan Cheng
d30bf01e90
Vector op lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:11:20 +00:00
Evan Cheng
f338dd881f
New type v2f32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26435 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:06:22 +00:00
Evan Cheng
aafc1412b1
Another entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26430 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 23:38:49 +00:00
Evan Cheng
8c03fe4aca
Don't match x << 1 to LEAL. It's better to emit x + x.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 21:13:57 +00:00
Chris Lattner
bf751e2d6f
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
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but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 07:08:22 +00:00
Chris Lattner
f4c8575c27
remove implemented item
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:36:04 +00:00
Nate Begeman
6e53ceb0d4
readme updates
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 22:08:36 +00:00
Chris Lattner
a34544d96c
Don't print constant initializers, they may span lines now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 20:09:23 +00:00
Jim Laskey
dae29989cf
Removed dependency on how operands are printed (want multi-line.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 10:29:04 +00:00
Evan Cheng
140a4c4868
ConstantPoolIndex is now the displacement portion of the address (rather
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than base).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 09:12:34 +00:00
Evan Cheng
a09bd8190c
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
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and 2005-05-12-Int64ToFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 08:28:12 +00:00
Evan Cheng
51a9ed9b41
* Cleaned up addressing mode matching code.
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* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:09:08 +00:00
Evan Cheng
53f280a30e
Updates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:04:07 +00:00
Evan Cheng
71fb834b50
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
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* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:02:21 +00:00
Evan Cheng
c4ee50c6b9
ConstantPoolIndex is now the displacement field of addressing mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26373 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 09:56:50 +00:00
Evan Cheng
bbbb2fbbde
Added a common about the need for X86ISD::Wrapper.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 09:55:19 +00:00
Evan Cheng
404cb4f9fa
Added an offset field to ConstantPoolSDNode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 09:54:52 +00:00
Evan Cheng
cb4a38e75d
Fix an obvious bug exposed when we are doing
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ADD X, 4
==>
MOV32ri $X+4, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 01:37:02 +00:00
Chris Lattner
2c003e26e5
Add memory printing support for PPC. Input memory operands now work with
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inline asms! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 20:27:40 +00:00
Chris Lattner
e5d8861126
Implement selection of inline asm memory operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 02:13:12 +00:00
Evan Cheng
d0839f3071
PPC JIT relocation model should be DynamicNoPIC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26338 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 22:18:07 +00:00
Evan Cheng
020d2e8e7a
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 20:41:18 +00:00
Chris Lattner
e3f01570c1
Implement the PPC inline asm "L" modifier. This allows us to compile:
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long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 19:31:10 +00:00
Chris Lattner
e650a6b3f4
"." isn't enough to get a private label on linux, use ".L".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26327 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 05:25:02 +00:00
Chris Lattner
205065ae0c
add a small and simple case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26326 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 05:17:43 +00:00
Evan Cheng
3032410f9b
A couple of new entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26325 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 02:50:21 +00:00
Evan Cheng
a0ea0539e3
PIC related bug fixes.
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1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 02:43:52 +00:00
Evan Cheng
224ec39cab
X86 codegen tweak to use lea in another case:
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Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26323 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 00:13:58 +00:00
Evan Cheng
f1616dadad
Missing .globl for weak / link-once .text symbols.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26321 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 23:59:57 +00:00
Evan Cheng
4c1aa86657
- Added option -relocation-model to set relocation model. Valid values include static, pic,
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dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 20:19:42 +00:00
Jim Laskey
0420f2aaf9
Coordinate activities with llvm-gcc4 and dwarf.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 19:02:11 +00:00
Evan Cheng
470a6adc78
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
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Fixed some existing bugs (wrong predicates, prefixes) at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 02:26:30 +00:00
Chris Lattner
1efa40f6a4
split register class handling from explicit physreg handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 00:56:39 +00:00
Chris Lattner
4217ca8dc1
Updates to match change of getRegForInlineAsmConstraint prototype
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 23:11:00 +00:00
Evan Cheng
4e4c71e423
One more round of reorg so sabre doesn't freak out. :-)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 20:00:20 +00:00
Evan Cheng
beb07e117d
A big more cleaning up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:30:30 +00:00
Evan Cheng
bf156d1ae6
Moving things to their proper places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:26:52 +00:00
Evan Cheng
ffcb95beab
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:13:53 +00:00
Chris Lattner
a1532bc283
missed optzn
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26299 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 18:29:44 +00:00
Chris Lattner
2deb87f201
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
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instructions are expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26298 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 18:04:32 +00:00
Evan Cheng
747a90d887
Added separate alias instructions for SSE logical ops that operate on non-packed types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26297 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 02:24:38 +00:00
Evan Cheng
7dbc0a3351
Added MMX and XMM packed integer move instructions, movd and movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26296 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 01:39:57 +00:00
Evan Cheng
933be3318b
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
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Added generic vector types: VR64 and VR128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 01:38:21 +00:00
Evan Cheng
aea20f50e5
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-20 22:34:53 +00:00
Evan Cheng
755ee8f9aa
Some updates
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26292 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-20 19:58:27 +00:00
Evan Cheng
45af8fd8c2
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
...
advantage of fisttpll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 07:26:17 +00:00
Evan Cheng
2b15271571
Added fisttp for fp to int conversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26283 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 02:36:28 +00:00
Evan Cheng
6428302f3d
Disable PIC for JIT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26281 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 01:49:25 +00:00
Evan Cheng
5e8b5558f7
Jit does not support PIC yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26278 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 00:57:10 +00:00
Evan Cheng
7ccced634a
x86 / Darwin PIC support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 00:15:05 +00:00
Evan Cheng
d2ee218b49
Moved PICEnabled to include/llvm/Target/TargetOptions.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 00:08:58 +00:00
Chris Lattner
c2fe97e726
unbreak the build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 07:09:27 +00:00
Evan Cheng
5298bcc722
Unbreak x86 be
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 07:01:52 +00:00
Nate Begeman
551bf3f800
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 05:43:56 +00:00
Chris Lattner
a648df2871
add note about div by power of 2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 04:20:13 +00:00
Nate Begeman
9c3c2e9686
Whoops, didn't mean to check this in yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26250 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:56:19 +00:00
Nate Begeman
c22f357b78
Add a missing and useful pat frag
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26249 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:51:06 +00:00
Evan Cheng
7634ac4a9b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
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issue. Need to do more experiments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:04:28 +00:00
Nate Begeman
4c5dcf54ff
Kill the x86 pattern isel. boom.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:03:04 +00:00
Evan Cheng
dc8acb6420
Remove the entry about using movapd for SSE reg-reg moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26245 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:00:58 +00:00
Evan Cheng
39d1761c70
pxor (for FLD0SS) encoding was missing the OpSize prefix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26244 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 23:59:30 +00:00
Chris Lattner
6a6eb7b622
Remove the skeleton target, it doesn't produce useful code and there are
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other small targets that do that can be learned from. They also have
the added advantage of being tested :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26243 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 23:14:50 +00:00
Evan Cheng
fe5cb19405
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
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proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26241 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 22:45:17 +00:00
Evan Cheng
19ade3bf9c
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26240 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 21:20:26 +00:00
Nate Begeman
368e18d56a
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 21:11:51 +00:00
Evan Cheng
77dea9b3c3
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26234 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 19:34:41 +00:00
Duraid Madina
00d3d44b75
distinguish between objects and register names, now we can have stuff
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with names like "f84", "in6" etc etc.
this should fix one or two tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 13:12:57 +00:00
Evan Cheng
298ebf2bd8
If the false case is the current basic block, then this is a self loop.
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We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 08:27:56 +00:00
Evan Cheng
d51425a82d
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
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transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26226 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 01:50:02 +00:00
Evan Cheng
18a8452f3d
A bit more memset / memcpy optimization.
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Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 00:21:07 +00:00
Evan Cheng
fe1c31204e
Remove an entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26222 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 22:14:34 +00:00
Chris Lattner
5946fef1db
new test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26217 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 19:52:06 +00:00
Chris Lattner
45090476be
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
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it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26204 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 07:07:14 +00:00
Chris Lattner
6fa1f57c66
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
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The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26202 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 06:41:34 +00:00
Evan Cheng
2354f5a46b
Remove an entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26197 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 01:56:48 +00:00
Evan Cheng
17ef92eda7
Use .zerofill on x86/darwin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26196 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 01:56:23 +00:00
Evan Cheng
f3f0a9c587
cvtsd2ss / cvtss2sd encoding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26193 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 00:31:03 +00:00
Evan Cheng
7335f9beea
movaps, movapd encoding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26192 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 00:11:37 +00:00
Chris Lattner
ae302ab9cb
new note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26186 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 22:19:54 +00:00
Chris Lattner
0d7db6f79a
If we have zero initialized data with external linkage, use .zerofill to
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emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26185 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 22:18:23 +00:00
Evan Cheng
ee50a1ae27
Don't special case XS, XD prefixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26183 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 21:52:51 +00:00