Commit Graph

37 Commits

Author SHA1 Message Date
Evan Cheng
506049f29f - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:44:33 +00:00
Jakob Stoklund Olesen
30ac0467ce Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06 23:47:07 +00:00
Chris Lattner
7896c9f436 improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03 00:50:42 +00:00
Evan Cheng
39aa7251a2 Check if subreg index is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88899 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 06:31:49 +00:00
Evan Cheng
d57cdd5683 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:55:43 +00:00
Evan Cheng
78e5c1140a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 03:52:02 +00:00
Evan Cheng
ff89dcb06f -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 18:16:27 +00:00
Evan Cheng
20270c9093 Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 06:27:36 +00:00
Evan Cheng
6553155172 Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17 07:53:04 +00:00
Evan Cheng
bf125583f8 Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17 06:22:26 +00:00
Dale Johannesen
3a6b9eb868 Revert the kludge in 76703. I got a clean
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 18:49:00 +00:00
Dan Gohman
a70dca156f Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:27:56 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Dan Gohman
28f02fdd76 Change MachineMemOperand's alignment value to be the alignment of
the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 19:47:04 +00:00
Evan Cheng
fc6ad402fb Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 00:25:27 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 09:20:10 +00:00
Evan Cheng
34c75093f0 Use findCommutedOpIndices to find the operands to commute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75312 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 23:26:12 +00:00
Evan Cheng
261ce1d5f8 Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 19:15:51 +00:00
Evan Cheng
498c2903e2 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 08:29:08 +00:00
Bill Wendling
587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
Bill Wendling
d62e06c53b Explicitly pass in debug location information to BuildMI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63599 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 02:29:34 +00:00
Dan Gohman
c54baa2d43 Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:43:12 +00:00
Dan Gohman
d735b8019b Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03 15:45:36 +00:00
Dan Gohman
014278e6a1 Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-13 17:58:21 +00:00
Evan Cheng
3885578a36 Fix a 80 column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56097 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-11 05:58:06 +00:00
Owen Anderson
44eb65cf58 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-14 22:49:33 +00:00
Dan Gohman
8e5f2c6f65 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07 23:14:23 +00:00
Evan Cheng
58dcb0e0cd Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 07:33:11 +00:00
Nicolas Geoffray
52e724ad7e Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 20:10:13 +00:00
Evan Cheng
ca1267c02b Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-31 20:40:39 +00:00
Evan Cheng
f20db15954 Added CommuteChangesDestination(). This returns true if commuting the specified
machine instr will change its definition register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-15 18:21:33 +00:00
Evan Cheng
9cec00e7f1 Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47058 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 09:13:21 +00:00
Evan Cheng
a4d16a1f0d commuteInstr() can now commute non-ssa machine instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 02:46:49 +00:00
Chris Lattner
749c6f6b5e rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 07:27:27 +00:00
Chris Lattner
8ca5c67c6e Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 02:39:19 +00:00
Chris Lattner
69244300b8 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 01:56:04 +00:00
Chris Lattner
6410552250 Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 01:03:04 +00:00