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788 Commits

Author SHA1 Message Date
Jim Grosbach
ec04a3f8db ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:49:24 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Jim Grosbach
8d11c6349f ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff ARM assembler support for the target-specific .req directive. 
rdar://10549683


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1 ARM LDM/STM system instruction variants. 
rdar://10550269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf Test for 146516 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207 ARM NEON two-operand aliases for VQDMULH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc ARM pre-UAL NEG mnemonic for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:23:22 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 22:02:17 +00:00
Jim Grosbach
a4e3c7fc4b ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 21:28:25 +00:00
Jim Grosbach
8759c3f548 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:06:06 +00:00
Jim Grosbach
318df74104 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d ARM VSUB implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be Tidy up. Move MachO tests to MachO directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
18851edbc4 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:56:05 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d Update tests for r145860. Add a few new ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:21:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
c4f0b309ee ARM tests for VLD1 single lane w/ writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:03:52 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jim Grosbach
e30171ba0c Add some tests for all-lanes VLD1 parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:37:38 +00:00
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Jim Grosbach
ed1f83f9af Enable some VST1 tests and add a few more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:40:32 +00:00
Chris Lattner
d2bf432b2b Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 06:54:59 +00:00
Jim Grosbach
9b1671bae7 Remove obsolete test. 
The PLD encoding is checked via the .s file now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:50:38 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:48:37 +00:00
Jim Grosbach
47a906ac23 Update test for r144842. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:46:27 +00:00