Jakob Stoklund Olesen
52346e964f
Heed spill slot alignment on ARM.
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Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:15:04 +00:00
Akira Hatanaka
05c585319b
Revert part of r146995 that was accidentally commmitted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:09:36 +00:00
Akira Hatanaka
403992dc58
32-to-64-bit sign extension pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:06:20 +00:00
Akira Hatanaka
caace8abdf
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
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only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 21:50:49 +00:00
Jim Grosbach
5b484312c6
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
Lang Hames
aa13482784
Fix assert condition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:23:40 +00:00
Jakub Staszak
25101bb2a7
Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:10 +00:00
Jim Grosbach
514806b52e
ARM enable a few more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:00 +00:00
Devang Patel
45ca049f1f
Add support to add named metadata operand.
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Patch by Andrew Wilkins!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:29:36 +00:00
Jim Grosbach
95fad1c603
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b
First steps in ARM AsmParser support for .eabi_attribute and .arch
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(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 17:38:12 +00:00
Elena Demikhovsky
ba4f83b4e9
This is the second fix related to VZEXT_MOVL node.
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The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb
Begin teaching the X86 target how to efficiently codegen patterns that
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use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 11:19:37 +00:00
Manuel Klimek
093147abf4
Fixes a potential compilation error.
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Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 11:04:23 +00:00
Manuel Klimek
9ce6937701
Pulls the implementation of skip() into JSONParser.
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This is the first step towards migrating more of the parser
implementation into the parser class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 10:42:52 +00:00
Manuel Klimek
2c777c8f86
Fixing option for JSON benchmark broken since the change to size_t.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 10:34:29 +00:00
Manuel Klimek
c4850c9a06
Addressing style issues in JSON parser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 09:26:26 +00:00
Chandler Carruth
cfb75fba73
Fix up the CMake build for the new files added in r146960, they're
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likely to stay either way that discussion ends up resolving itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:42:11 +00:00
David Blaikie
0c271bccf7
Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:22:49 +00:00
Nadav Rotem
7559766c63
Add a few lines to the release notes:
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1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:02:50 +00:00
David Blaikie
2d24e2a396
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 02:50:00 +00:00
Andrew Trick
1885687462
Unit test for r146950: LSR postinc expansion, PR11571.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:43:20 +00:00
Andrew Trick
ba3c0bc364
LSR: Fix another corner case in expansion of postinc users.
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Fixes PR11571: Instruction does not dominate all uses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146950 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:42:24 +00:00
Bob Wilson
c0b0e57a87
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
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We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:29:27 +00:00
Chris Lattner
b5e8b8c8f7
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:11:37 +00:00
Dan Gohman
eb4c70b9c4
Add a line to ReleaseNotes for half float.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:10:56 +00:00
Jim Grosbach
04b5d93250
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:59:38 +00:00
Chris Lattner
ea93373a0a
Now that PR11464 is fixed, reapply the patch to fix PR11464,
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merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:12:26 +00:00
Chris Lattner
68910509fd
fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:03:52 +00:00
Chris Lattner
f5c9bd07bc
add a method to improve compatibility with SmallVector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:03:41 +00:00
Dan Gohman
e3376ecd50
Add basic generic CodeGen support for half.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:02:33 +00:00
Jim Grosbach
9b0878512f
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
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e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117 "
rdar://10603913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:51:07 +00:00
Evan Cheng
26118cfaa0
Move tests to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:26:44 +00:00
Jim Grosbach
2f196747f1
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:06:24 +00:00
Evan Cheng
8787c5f24e
Add a if-conversion optimization that allows 'true' side of a diamond to be
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unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 22:01:30 +00:00
Eli Friedman
638905d90c
Add "using" to silence warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 21:53:12 +00:00
Akira Hatanaka
59eb8056e0
Add a test case for r146900.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:24:28 +00:00
Akira Hatanaka
f06cb2b207
Add patterns for matching immediates whose lower 16-bit is cleared. These
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patterns emit a single LUi instruction instead of a pair of LUi and ORi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:21:18 +00:00
Eli Friedman
1e2ec6abd4
Attempt to fix PR11607 by shuffling around which class defines which methods.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:06:03 +00:00
Akira Hatanaka
8209968306
Tidy up. Simplify logic. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:52:25 +00:00
Jim Grosbach
d22170e16a
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:51:03 +00:00
Akira Hatanaka
ee973147ac
Remove definitions of double word shift plus 32 instructions. Assembler or
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direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:44:09 +00:00
Jim Grosbach
6849019079
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:43:50 +00:00
Akira Hatanaka
ed538b5271
Remove unused predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:32:20 +00:00
Akira Hatanaka
89dc8d790d
Remove the restriction on the first operand of the add node in SelectAddr.
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This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:28:37 +00:00
Jim Grosbach
9c39789c36
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:02:41 +00:00
Jim Grosbach
61b74b4247
ARM NEON implied destination aliases for VMAX/VMIN.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:31:43 +00:00
Jim Grosbach
3346dcef02
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:11:17 +00:00