Commit Graph

509 Commits

Author SHA1 Message Date
David Greene
8a34229dcf Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-04 22:49:02 +00:00
Lang Hames
74ab5eeffb Changed slot index ranges for MachineBasicBlocks to be exclusive of endpoint.
This fixes an in-place update bug where code inserted at the end of basic blocks may not be covered by existing intervals which were live across the entire block. It is also consistent with the way ranges are specified for live intervals.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91859 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 00:11:50 +00:00
Jakob Stoklund Olesen
74215fc29f Reuse lowered phi nodes.
Tail duplication produces lots of identical phi nodes in different basic
blocks. Teach PHIElimination to reuse the join registers when lowering a phi
node that is identical to an already lowered node. This saves virtual
registers, and more importantly it avoids creating copies the the coalescer
doesn't know how to eliminate.

Teach LiveIntervalAnalysis about the phi joins with multiple uses.

This patch significantly reduces code size produced by -pre-regalloc-taildup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 18:55:53 +00:00
Evan Cheng
ac94863a1c Coalesce insert_subreg undef, x first to avoid phase ordering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91103 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 06:01:00 +00:00
Jakob Stoklund Olesen
cf97036675 Also attempt trivial coalescing for live intervals that end in a copy.
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch is more conservative than r90502, and does not break
483.xalancbmk/i686. It still breaks the PowerPC bootstrap, so it is disabled
by default, and can be enabled with the -trivial-coalesce-ends option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-10 17:48:32 +00:00
Lang Hames
6194569d22 Added a new "splitting" spiller.
When a call is placed to spill an interval this spiller will first try to
break the interval up into its component values. Single value intervals and
intervals which have already been split (or are the result of previous splits)
are spilled by the default spiller.

Splitting intervals as described above may improve the performance of generated
code in some circumstances. This work is experimental however, and it still
miscompiles many benchmarks. It's not recommended for general use yet.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90951 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 05:39:12 +00:00
Bill Wendling
dc492e0370 Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90653 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 07:30:23 +00:00
Jakob Stoklund Olesen
6b74e505be Also attempt trivial coalescing for live intervals that end in a copy.
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch takes care of a few more cases that r90163 missed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-04 00:16:04 +00:00
Jakob Stoklund Olesen
f4811a9694 Clean up some loop logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90481 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03 20:49:10 +00:00
Evan Cheng
9836a26da3 Fix PR5391: support early clobber physical register def tied with a use (ewwww)
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90269 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 22:25:00 +00:00
Jakob Stoklund Olesen
ce7a663140 New virtual registers created for spill intervals should inherit allocation hints from the original register.
This helps us avoid silly copies when rematting values that are copied to a physical register:

leaq	_.str44(%rip), %rcx
movq	%rcx, %rsi
call	_strcmp

becomes:

leaq	_.str44(%rip), %rsi
call	_strcmp

The coalescer will not touch the movq because that would tie down the physical register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30 22:55:54 +00:00
Jakob Stoklund Olesen
6cd8103bea More consistent labelling of basic blocks in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89470 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 18:54:59 +00:00
Jakob Stoklund Olesen
324da7647c Add MachineBasicBlock::getName, and use it in place of getBasicBlock()->getName.
Fix debug code that assumes getBasicBlock never returns NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 01:17:03 +00:00
Jakob Stoklund Olesen
1e78aa445c Remove the -early-coalescing option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89240 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 20:36:47 +00:00
Evan Cheng
df8ed02473 Hide a couple of options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 06:49:37 +00:00
Jakob Stoklund Olesen
3de23e6f6c Fix inverted conflict test in -early-coalesce.
A non-identity copy cannot be coalesced when the phi join destination register
is live at the copy site.

Also verify the condition that the PHI join source register is only used in
the PHI join. Otherwise the coalescing is invalid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86322 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 01:58:40 +00:00
Lang Hames
233a60ec40 The Indexes Patch.
This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.

For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.

The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85979 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 23:52:08 +00:00
Evan Cheng
5f4fb86d58 Trim unnecessary includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84597 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 04:23:20 +00:00
Evan Cheng
0222a8cfb8 If the physical register being spilled does not have an interval, spill its sub-registers instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84586 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:31:09 +00:00
Dan Gohman
a70dca156f Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:27:56 +00:00
Dan Gohman
599a87aca0 isTriviallyReMaterializable checks the
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 21:02:10 +00:00
Dan Gohman
2627e08e05 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and
teach it how to recognize invariant physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83476 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 17:47:20 +00:00
Lang Hames
6cc91e39c0 Oops. Renamed remaining MachineInstrIndex references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-03 04:31:31 +00:00
Lang Hames
cc3b0650f1 Renamed MachineInstrIndex to LiveIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83254 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-03 04:21:37 +00:00
Daniel Dunbar
295a8089cd Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82821 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 23:26:56 +00:00
Dan Gohman
2bf0649e05 Simplify a few more uses of reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 22:26:13 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Evan Cheng
296925dc16 Fix PR5024. LiveVariables physical register defs should *commit* only after all
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 06:28:31 +00:00
Evan Cheng
b0f5973bee Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 04:32:32 +00:00
Dale Johannesen
39faac2531 When computing live intervals for earlyclobber operands,
we pushed the beginning of the interval back 1, so the
interval would overlap with inputs that die.  We were
also pushing the end of the interval back 1, though,
which means the earlyclobber didn't overlap with other
output operands.  Don't do this.  PR 4964.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82342 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-20 00:36:41 +00:00
Daniel Dunbar
504f9a61e6 Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 20:31:12 +00:00
Evan Cheng
3f85549f4d Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies.
Still miscompiling some tests. :-(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81849 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 06:45:16 +00:00
Evan Cheng
752195e3c6 Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this.
The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81796 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-14 21:33:42 +00:00
Lang Hames
35f291d2c5 Moved some more index operations over to LiveIntervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81605 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12 03:34:03 +00:00
Evan Cheng
217311130d 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12 02:01:07 +00:00
Lang Hames
8651125d28 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with
a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81040 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-04 20:41:11 +00:00
Chris Lattner
45cfe545ec Change Pass::print to take a raw ostream instead of std::ostream,
update all code that this affects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79830 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 06:03:38 +00:00
Chris Lattner
705e07f578 remove various std::ostream version of printing methods from
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 03:41:05 +00:00
Chris Lattner
77942d4ee4 remove a dead class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79795 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 00:42:42 +00:00
Bill Wendling
8e6179fb13 Convert DOUT to DEBUG(errs()...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79752 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22 20:18:03 +00:00
Lang Hames
52c1afcaea Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 23:43:28 +00:00
Evan Cheng
6ade93bbdc Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78151 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 03:53:14 +00:00
David Greene
b525766479 Re-apply LiveInterval index dumping patch, with fixes suggested by Bill
and others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78003 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 21:55:09 +00:00
Dan Gohman
845012e6d3 Use setPreservesAll and setPreservesCFG in CodeGen passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77754 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 23:37:33 +00:00
Daniel Dunbar
ce63ffb52f More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:23:56 +00:00
Daniel Dunbar
3f0e83067d Move to raw_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76963 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 09:53:24 +00:00
David Greene
340482dcc0 Constify the key in Mi2IndexMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76801 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 21:56:14 +00:00
Chris Lattner
3380d5c4aa revert r76602, 76603, and r76615, pending design discussions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76646 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 21:12:58 +00:00
David Greene
a358c1db5c Prefix IR dumps with LiveInterval indices when possible. This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76615 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 18:56:32 +00:00
Evan Cheng
d129d73b72 Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 19:43:40 +00:00