Meador Inge
6098c6b56b
Add more functions to the target library information.
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I discovered a few more missing functions while migrating optimizations
from the simplify-libcalls pass to the instcombine (I already added some
in r167659).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-22 15:36:42 +00:00
Jack Carter
198ad916d7
Mips direct object xgot support
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This patch provides support for the MIPS relocations:
*) R_MIPS_GOT_HI16
*) R_MIPS_GOT_LO16
*) R_MIPS_CALL_HI16
*) R_MIPS_CALL_LO16
These are used for large GOT instruction sequences.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 23:38:59 +00:00
Akira Hatanaka
f09a03776d
[mips] Generate big GOT code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:40:38 +00:00
Akira Hatanaka
d43e06de59
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper
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functions added in r168456.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:30:40 +00:00
Akira Hatanaka
6b28b80791
[mips] Add helper functions that create nodes for computing address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:26:38 +00:00
Akira Hatanaka
81784cb374
[mips] Add command line option "-mxgot".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:21:11 +00:00
Akira Hatanaka
59be760f61
[mips] When a node which loads from a GOT is created, pass a MachinePointerInfo
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referring to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:16:34 +00:00
Jyotsna Verma
b546d5a30d
Add new predicates for the immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:05:09 +00:00
Akira Hatanaka
26e6ad7b29
[mips] Add target operand flag enums for big GOT relocations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168450 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 19:59:51 +00:00
Jyotsna Verma
81081b16ef
Use one common 'let' expression to set PrintMethod for all immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168449 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 19:53:42 +00:00
Anton Korobeynikov
0ae6124034
Add support for varargs functions for msp430.
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Patch by Job Noorman!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 17:28:27 +00:00
Anton Korobeynikov
6cbeb4d839
Add support for byval args. Patch by Job Noorman!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 17:23:03 +00:00
Rafael Espindola
6ee1e0867d
Finish the renaming.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 16:56:33 +00:00
Jyotsna Verma
24d5025d8d
Renamed HexagonImmediates.td -> HexagonOperands.td.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 16:28:18 +00:00
Craig Topper
9648782552
Fix execution domain for packed FMA4 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 08:08:21 +00:00
Craig Topper
3dcefc864e
Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so that llvm.muladd can be converted to ISD::FMA for fp_contract.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168413 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 05:36:24 +00:00
Jakub Staszak
e845cedf4d
Make calcLiveInMask method static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 00:59:34 +00:00
Jakub Staszak
6f05f21857
Make isScratchReg and isFPCopy methods static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168407 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 00:50:57 +00:00
Jakub Staszak
8c67c03b0c
Add obvious constantness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20 23:32:32 +00:00
Jyotsna Verma
7d1b42a842
Removing some unused instruction definitions from the Hexagon backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20 22:14:23 +00:00
Elena Demikhovsky
4fe5405bdd
Intel OCL built-ins calling conventions now support MacOS 32-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20 09:37:57 +00:00
Eli Friedman
43147afd71
Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17 01:52:46 +00:00
Akira Hatanaka
94e472832f
Initial implementation of MipsTargetLowering::isLegalAddressingMode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17 00:25:41 +00:00
Weiming Zhao
8b149cbfc6
Rename methods like PairSRegs() to createSRegpairNode() to meet our coding
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style requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168229 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17 00:23:35 +00:00
Weiming Zhao
e56764bad1
Remove hard coded registers in ARM ldrexd and strexd instructions
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This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:55:34 +00:00
Anton Korobeynikov
b1a392e7c5
Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
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This fixes PR14359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:15:20 +00:00
Richard Osborne
ccc015d431
Fix handling of aliases to functions.
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An alias to a function should use pc relative addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:12:38 +00:00
Justin Holewinski
2085d00d09
[NVPTX] Order global variables in def-use order before emiting them in the final assembly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168198 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:03:51 +00:00
Joe Abbey
48f63be368
Using const cast to alleviate a warning.
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A PR is being filed to address some code issues here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 19:38:42 +00:00
Duncan Sands
dc7f174b5e
Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 12:36:39 +00:00
Craig Topper
d577552c66
Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 06:37:56 +00:00
Akira Hatanaka
a032dbd62f
[mips] Fix delay slot filler so that instructions with register operand $1 are
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allowed in branch delay slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 02:39:34 +00:00
Eli Friedman
846ce8ea67
Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
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case to vector legalization so this actually works.
Patch by Pete Couperus. Fixes PR12540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 22:44:27 +00:00
Akira Hatanaka
0301bc54ad
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
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support and use it in place of HasMips32r2Or64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 21:17:13 +00:00
Adhemerval Zanella
e95ed2b7af
PowerPC: Lowering floor intrinsic for Altivec
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This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 20:56:03 +00:00
Akira Hatanaka
c984657c74
Add assertions in MipsLongBranch which check the size of basic blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 20:05:11 +00:00
Jakub Staszak
1c1c49372c
Return 0 instead of false.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 19:40:29 +00:00
Jakub Staszak
eaf77254d4
Simplify code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 19:05:23 +00:00
Dmitri Gribenko
79c07d2a36
Use empty parens for empty function parameter list instead of '(void)'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 16:51:49 +00:00
Craig Topper
116bd168e1
Revert changing FNEG of v4f32 to Expand. It's legal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 08:09:46 +00:00
Craig Topper
b916904e68
Make FNEG and FABS of v4f32 Expand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 08:06:12 +00:00
Craig Topper
44e394cf61
Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 08:02:19 +00:00
Craig Topper
490104720d
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 06:51:10 +00:00
Jakub Staszak
3427f0aa7c
Remove unneeded #includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 23:58:57 +00:00
NAKAMURA Takumi
e8b0ae1fb6
NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 23:46:15 +00:00
Eric Christopher
06b423452c
Remove the CellSPU port.
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Approved by Chris Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 22:09:20 +00:00
Jakub Staszak
7454fc2e87
Fix invalid asserts, use llvm_unreachable instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 21:03:40 +00:00
Jyotsna Verma
cb02fa9d7f
Added multiclass for post-increment load instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:38:48 +00:00
Benjamin Kramer
2dbe929685
X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes.
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The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.
Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.
Effectively reverts r58317. Part of PR2962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:08:40 +00:00
Nadav Rotem
50b66387e3
The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
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This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.
rdar://12028498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 19:39:15 +00:00
Justin Holewinski
a20067b5d4
[NVPTX] Implement custom lowering of loads/stores for i1
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Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8
Fixes PR13291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 19:19:16 +00:00
Jim Grosbach
3ca6382120
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.
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When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 18:04:47 +00:00
Craig Topper
1ab489a42d
Set FFLOOR of vectors to expand to keep intruction selection from failing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 08:11:25 +00:00
Craig Topper
55de339dad
Factor out an overly replicated typecast. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 06:41:09 +00:00
Craig Topper
509bd72576
Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 05:56:30 +00:00
Anton Korobeynikov
25efd6d556
Use TARGET2 relocation for TType references on ARM.
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Do some cleanup of the code while here.
Inspired by patch by Logan Chien!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 01:47:00 +00:00
Ulrich Weigand
ba6086818d
Add (some) PowerPC TLS relocation types to ELF.h and
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generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:24:36 +00:00
Ulrich Weigand
8f887369cb
Fix wrong PowerPC instruction opcodes for:
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- lwaux
- lhzux
- stbu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:21:31 +00:00
Ulrich Weigand
4ff09818a9
Fix wrong PowerPC instruction encodings due to
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operand field name mismatches in:
- AForm_3 (fmul, fmuls)
- XFXForm_5 (mtcrf)
- XFLForm (mtfsf)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:19:46 +00:00
Ulrich Weigand
18430436ca
Fix instruction encoding for "bd(n)z" on PowerPC,
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by using a new instruction format BForm_1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:15:52 +00:00
Ulrich Weigand
bc40df3f22
Fix instruction encoding for "isel" on PowerPC,
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using a new instruction format AForm_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:14:19 +00:00
Manman Ren
2adc503f29
X86: when constructing VZEXT_LOAD from other loads, makes sure its output
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chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://12684358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:13:05 +00:00
Andrew Trick
ad1cc1d1bf
misched: Allow subtargets to enable misched and dependent options.
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This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.
Disabling PostRA sched may follow for some subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 08:47:29 +00:00
Jyotsna Verma
266c473b91
Test commit.
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Add a blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 06:31:55 +00:00
Andrew Trick
9b5caaa9c4
misched: Target-independent support for load/store clustering.
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This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.
A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 19:40:10 +00:00
Ulrich Weigand
95d8afc5f2
Make TOC order deterministic by using MapVector instead of DenseMap.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 19:13:24 +00:00
Eric Christopher
4db8833c93
Remove unused field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 07:35:12 +00:00
Michael Liao
dd3383fd09
Fix PR14314
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- Fix operand order for atomic sub, where the minuend is the value
loaded from memory and the subtrahend is the parameter specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 06:49:17 +00:00
Justin Holewinski
08e9cb46fe
[NVPTX] Add more precise PTX/SM target attributes
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Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally,
PTX 3.1 is added as the default PTX version to be out-of-the-box compatible
with CUDA 5.0.
Available CPUs for this target:
sm_10 - Select the sm_10 processor.
sm_11 - Select the sm_11 processor.
sm_12 - Select the sm_12 processor.
sm_13 - Select the sm_13 processor.
sm_20 - Select the sm_20 processor.
sm_21 - Select the sm_21 processor.
sm_30 - Select the sm_30 processor.
sm_35 - Select the sm_35 processor.
Available features for this target:
ptx30 - Use PTX version 3.0.
ptx31 - Use PTX version 3.1.
sm_10 - Target SM 1.0.
sm_11 - Target SM 1.1.
sm_12 - Target SM 1.2.
sm_13 - Target SM 1.3.
sm_20 - Target SM 2.0.
sm_21 - Target SM 2.1.
sm_30 - Target SM 3.0.
sm_35 - Target SM 3.5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 03:16:43 +00:00
Craig Topper
2da3691d6d
Move some helper methods to being static functions in the implementation file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-11 22:45:02 +00:00
Nadav Rotem
955cf53266
Use the isTruncFree and isZExtFree API to figure out of these operations are free. Thanks Andy!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-11 05:34:45 +00:00
Craig Topper
52ea245083
Remove unnecessary subtraction and addition by 1 around a couple for loops.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 09:25:36 +00:00
Craig Topper
8cb8c8119a
Tidy up spacing. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 09:02:47 +00:00
Craig Topper
5ed5c37d7f
Removed unimplemented method declaration.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 09:00:12 +00:00
Craig Topper
8aae8ddb92
Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper functions static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 08:57:41 +00:00
Meador Inge
939f500202
Add more functions to the target library information.
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In the process of migrating optimizations from the simplify-libcalls pass
to the instcombine pass I noticed that a few functions are missing from
the target library information. These functions need to be available for
querying in the instcombine library call simplifiers. More functions will
probably be added in the future as more simplifiers are migrated to
instcombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 03:11:06 +00:00
Evan Cheng
b341fac05a
Disable the Thumb no-return call optimization:
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mov lr, pc
b.w _foo
The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.
rdar://12663632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 02:09:05 +00:00
Craig Topper
9c7ae01f39
Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10 01:23:36 +00:00
Justin Holewinski
89443ff7ae
[NVPTX] Use ABI alignment for parameters when alignment is not specified.
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Affects SM 2.0+. Fixes bug 13324.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 23:50:24 +00:00
Anton Korobeynikov
12cfa11960
Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.
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Based on the patch by Logan Chien!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 20:20:12 +00:00
Roman Divacky
64f03673d2
Switch FreeBSD/i386 back to 4byte stack alignment. This partially
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reverts r126226.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 20:10:44 +00:00
Chad Rosier
b3235b128f
Revert r167620; this can be implemented using an existing CL option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 18:25:27 +00:00
Chad Rosier
d054eda441
Add support for -mstrict-align compiler option for ARM targets.
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rdar://12340498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 17:29:38 +00:00
Nadav Rotem
b14a5f5f95
indent
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 07:02:24 +00:00
Amara Emerson
214fd3d244
Recommit modified r167540.
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Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08 09:51:45 +00:00
Michael Liao
be02a90de1
Add support of RTM from TSX extension
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- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08 07:28:54 +00:00
Akira Hatanaka
e90a3bcae1
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
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Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 19:10:58 +00:00
Akira Hatanaka
7085221a59
Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167546 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 19:04:26 +00:00
Amara Emerson
162d91c1e0
Revert r167540 until regression tests are updated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 18:57:14 +00:00
Amara Emerson
19a1fcf868
Improve ARM build attribute emission for architectures types.
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This also changes the default architecture emitted for a generic CPU to "v7".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 18:01:03 +00:00
Chad Rosier
6aa6e5a285
[arm fast-isel] Appease the machine verifier by using the proper register
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classes. For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 00:13:01 +00:00
Jakub Staszak
dccd7f9187
Simplify code. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 23:52:19 +00:00
Nadav Rotem
d8eae8ba05
Make the helper functions static. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 23:36:00 +00:00
Chad Rosier
e7bd51980a
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
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registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.
Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 23:05:24 +00:00
Nadav Rotem
a6fb97a49a
CostModel: add another known vector trunc optimization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 21:17:17 +00:00
Nadav Rotem
b042868c01
Cost Model: add tables for some avx type-conversion hacks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167480 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 19:33:53 +00:00
Michael Liao
0f6a599434
Remove tailing whitespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 08:06:35 +00:00
Andrew Trick
a78d3228e8
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
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This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 03:13:46 +00:00
Nadav Rotem
887c1fe701
Refactor the getTypeLegalizationCost interface. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-05 23:57:45 +00:00
Nadav Rotem
7ae3bcca45
CostModel: Add tables for the common x86 compares.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-05 23:48:20 +00:00