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170 Commits

Author SHA1 Message Date
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Bob Wilson
8d4de5abfa Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:26:41 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:33:39 +00:00
Jim Grosbach
c732adf3a1 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:35:11 +00:00
Evan Cheng
cdf23b950a Remove comments which don't add much to .s readibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81306 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 01:38:23 +00:00
David Goodwin
e8d82c0e4f Calls clobber FPSCR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 22:12:28 +00:00
Evan Cheng
029599bf01 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80615 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-31 20:14:07 +00:00
Evan Cheng
d17479e845 Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 06:59:37 +00:00
Evan Cheng
0e87e23f6e v4, v5 does not support sxtb / sxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 00:31:43 +00:00
Bob Wilson
4f38b383d5 Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 21:58:55 +00:00
Evan Cheng
89d177f017 Fix an obvious copy-n-paste bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-20 17:01:04 +00:00
David Goodwin
5d598aaf3d Update Cortex-A8 instruction itineraries for integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-19 18:00:44 +00:00
Evan Cheng
51f39961c3 Fix revsh pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 05:43:23 +00:00
Evan Cheng
31b99dd760 Also shrink immediate branches; also more assembler workarounds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 18:31:44 +00:00
Evan Cheng
a1efbbdbf3 Shrink ADR and LDR from constantpool late during constantpool island pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 00:32:16 +00:00
David Goodwin
6d3d9c3fc3 Finalize itineraries for cortex-a8 integer multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:51:13 +00:00
David Goodwin
1a8f36e3ce Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 18:31:53 +00:00
Evan Cheng
007ea274f4 Shrink Thumb2 movcc instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 05:17:19 +00:00
Evan Cheng
c972165b11 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 02:03:03 +00:00
Evan Cheng
b89030ab65 Shrinkify Thumb2 r = add sp, imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 23:00:31 +00:00
Evan Cheng
4b322e58b7 Shrinkify Thumb2 load / store multiple instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 21:11:32 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:56:29 +00:00
Evan Cheng
e8af1f9afe Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 02:37:24 +00:00
Anton Korobeynikov
8e9ece75db Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 23:10:41 +00:00
Evan Cheng
57834cdee5 tADDhirr should target GPR, not tGPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78454 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:19:44 +00:00
Evan Cheng
53c67c0218 tBfar is bl, which clobbers LR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 05:45:07 +00:00
Evan Cheng
861986401e It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 00:34:42 +00:00
David Goodwin
8b7d7ade85 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 16:52:47 +00:00
Evan Cheng
35d6c41fde Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 23:47:55 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
Evan Cheng
20a2a0aff3 Make sure Thumb2 uses the right call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 21:26:42 +00:00
Evan Cheng
0531d04d00 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 20:10:36 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
David Goodwin
c9d138f505 Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 19:59:26 +00:00
Evan Cheng
d83360694a Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 23:59:01 +00:00
Evan Cheng
81c102ba66 Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:26:03 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Evan Cheng
756da12ae4 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:46:53 +00:00
Evan Cheng
4a8b7d030b Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76728 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:37:28 +00:00
Evan Cheng
3ecadc816d Do not select tSXTB / tSXTH in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 18:15:26 +00:00
Evan Cheng
a6e4322ccc Fix tSUBspi operand definition. It reads and writes sp, which is a high register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76155 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 05:43:12 +00:00
Evan Cheng
f6bc4ae4a1 1. In Thumb mode, select tBx instead of ARM variants. 
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 01:49:27 +00:00
Evan Cheng
2f297df02e Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Evan Cheng
892837abf3 We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 02:09:04 +00:00
Evan Cheng
06e16587eb Add a thumb2 pass to insert IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 01:54:42 +00:00
Evan Cheng
e5564748b7 Added Thumb IT instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75198 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 23:43:36 +00:00
David Goodwin
f1daf7d8ab Use common code for both ARM and Thumb-2 instruction and register info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:10:31 +00:00
David Goodwin
334c26473b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:09:28 +00:00
David Goodwin
5e47a9a6e4 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 18:04:13 +00:00
Evan Cheng
f3c21b857b A few more load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 02:15:48 +00:00
David Goodwin
c0309b48b5 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 07:51:04 +00:00
Evan Cheng
9cb9e6778c Renaming for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 02:26:13 +00:00
Evan Cheng
e864b74e95 tst is also commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74236 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 00:19:07 +00:00
David Goodwin
c9ee1189c5 Add Def/Use of CPSR for Thumb-1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 22:49:55 +00:00
David Goodwin
9a36bdbaf1 Test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74185 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 17:52:32 +00:00
Evan Cheng
7dcf4a826c Some reorg and additional comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74152 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 01:05:06 +00:00
Evan Cheng
a09b9ca10f Add Thumb2 pc relative add. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 23:47:58 +00:00
Evan Cheng
09c39fcf83 Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 19:38:13 +00:00
Bob Wilson
1c76d0ee5c Add explicit types for shift count constants. This is in preparation for 
another change that makes the types ambiguous (at least as far as tablegen
is concerned).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 22:08:29 +00:00
Eli Friedman
6b7bb42c36 Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 01:43:08 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 20:46:18 +00:00
Jim Grosbach
c93f961874 correct register class for tADDspi to GPR since the register will always be SP 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-12 22:30:18 +00:00
Jim Grosbach
30eae3c022 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-07 20:34:09 +00:00
Jim Grosbach
0ede14f5c0 remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 23:06:27 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 18:15:48 +00:00
Dan Gohman
f5aeb1a8e4 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 16:56:44 +00:00
Evan Cheng
130966411f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 06:41:12 +00:00
Chris Lattner
ddf89566a9 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-17 19:59:44 +00:00
Chris Lattner
9b37aaf04c get def use info more correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-10 05:12:37 +00:00
Evan Cheng
325474e065 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-07 23:56:57 +00:00
Chris Lattner
834f1ce031 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 23:38:27 +00:00
Chris Lattner
2e48a70b35 rename isStore -> mayStore to more accurately reflect what it captures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 08:36:04 +00:00
Chris Lattner
13c6310866 remove explicit isStore flags that are now inferrable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 05:55:01 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Bill Wendling
0f8d9c04d9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-13 00:44:25 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
f81dea45b5 tBcc is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:13:23 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
3f8602cf20 ARM::tB is also predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:43 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Evan Cheng
1b20168433 Doh. PC displacement is between the constantpool and the add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 20:27:19 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 13:54:47 +00:00
Evan Cheng
eec041a037 Back out previous check-in. Incorrect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:50:02 +00:00
Evan Cheng
33fdc983fd tLEApcrel is a AddrModeTs, i.e. pc relative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36502 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:37:22 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00