Commit Graph

95201 Commits

Author SHA1 Message Date
Craig Topper
5bdf397e25 Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 05:57:45 +00:00
Nadav Rotem
ec7b5e9290 In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.
Patch by Chris Bieneman.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 05:03:10 +00:00
Nadav Rotem
9397683e62 Add the FMA3 feature in order to test FMA encoding using the old jit.
Patch by Chris Bieneman!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 05:02:12 +00:00
Craig Topper
33b5fe7f16 Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 03:57:57 +00:00
NAKAMURA Takumi
d5a2eb0925 X86TargetMachine.cpp: Clarify to emit GOT in i686-{cygming|win32}-elf for mcjit.
I suppose all "lli -use-mcjit i686-*" should require GOT, (and to fail.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 02:37:25 +00:00
NAKAMURA Takumi
65566e1684 lli/RecordingMemoryManager.cpp: Make it complain if _GLOBAL_OFFSET_TABLE_ were not provided.
FIXME: Would it be responsible to provide GOT?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 02:37:14 +00:00
Jakub Staszak
0856d3d971 Move #includes from .h to .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188852 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 01:20:11 +00:00
Akira Hatanaka
d22b327b3d [micromips] Print instruction alias "not" if the last operand of a nor is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188851 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 01:18:46 +00:00
Bill Wendling
f675b3c644 Move registering the execution of a basic block to the beginning rather than the end.
There are situations which can affect the correctness (or at least expectation)
of the gcov output. For instance, if a call to __gcov_flush() occurs within a
block before the execution count is registered and then the program aborts in
some way, then that block will not be marked as executed. This is not normally
what the user expects.

If we move the code that's registering when a block is executed to the
beginning, we can catch these types of situations.

PR16893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:52:00 +00:00
Akira Hatanaka
b1f4f120a5 [mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:47:25 +00:00
Akira Hatanaka
ad341d48f0 [mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:38:40 +00:00
Akira Hatanaka
c89cb45ecb [mips] Remove predicates that were incorrectly or unnecessarily added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:21:55 +00:00
Jakub Staszak
328a4fbfbb Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:04:15 +00:00
Bill Wendling
815af99a04 Use -disable-output and to suppress output and don't use a temporary file unless we need one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:00:25 +00:00
Akira Hatanaka
3531db14c6 [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 22:58:56 +00:00
Jakub Staszak
5f560af541 Fix include guards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188841 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 22:52:02 +00:00
Arnold Schwaighofer
16a2253e40 SLPVectorizer: Fix invalid iterator errors
Update iterator when the SLP vectorizer changes the instructions in the basic
block by restarting the traversal of the basic block.

Patch by Yi Jiang!

Fixes PR 16899.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:21:45 +00:00
Matt Arsenault
80f495aab0 Teach ConstantFolding about pointer address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:20:04 +00:00
Akira Hatanaka
a98a486ad1 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:08:22 +00:00
Reed Kotler
0323d4b169 Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 20:53:09 +00:00
Akira Hatanaka
93877b3cbc [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 20:46:51 +00:00
Jim Grosbach
8b262e5ab8 ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 19:12:42 +00:00
Andrew Kaylor
11873fc85a Still more MCJIT PIC test XFAILs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 18:13:48 +00:00
Andrew Kaylor
17b06b899e Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 17:01:35 +00:00
Andrew Kaylor
c90825d1ae Removing duplicate XFAIL markers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 16:42:22 +00:00
Andrew Kaylor
58a81a1c62 Marking two more MCJIT PIC tests as XFAIL on i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 15:47:04 +00:00
Andrew Kaylor
2d219d67d2 Marking MCJIT PIC tests as XFAIL on arm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 15:36:04 +00:00
Vladimir Medic
7b0a79601b Fix style issues in AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 13:33:18 +00:00
Elena Demikhovsky
38cd21a3e9 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 11:00:29 +00:00
Daniel Sanders
c5158b869b [mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:41:47 +00:00
Richard Sandiford
0371d01fb9 [SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:40:35 +00:00
Richard Sandiford
8c20158fb0 [SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry.  I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.

This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA.  This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.

We should also try to optimize null checks so that they test the CC result
of the SRST directly.  The select between null and the SRST GPR result could
then usually be deleted as dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:38:48 +00:00
Benjamin Kramer
74e81aae7c memcmp is not a valid way to compare structs with padding in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:27:31 +00:00
Daniel Sanders
6ef333501e [mips][msa] Added insve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:22:54 +00:00
Richard Sandiford
7a4dd51e12 Fix test typo and add usual "br %r14" test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:14:46 +00:00
Richard Sandiford
9608ed1311 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:11:13 +00:00
Tim Northover
32c2bfda77 ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:57:11 +00:00
Michael Gottesman
ade3075030 [stackprotector] Small cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:28 +00:00
Michael Gottesman
d4f478899e [stackprotector] Small Bit of computation hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:26 +00:00
Michael Gottesman
b99272a521 [stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:23 +00:00
Michael Gottesman
c02dbeb429 Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:46:16 +00:00
Michael Gottesman
47d6e07a9b [stackprotector] Removed stale TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:46:13 +00:00
Daniel Sanders
c149fbbe27 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:38:21 +00:00
Michael Gottesman
3480d1b84e [stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://13935163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:36:53 +00:00
Michael Gottesman
9d6852cf98 [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.

rdar://13935163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:36:50 +00:00
Michael Gottesman
1a6de17273 Remove unused variables that crept in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 07:17:27 +00:00
Michael Gottesman
657484f494 Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).

Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!

A few goals in solving this problem were:

  1. Preserve the architecture independence of stack protector generation.

  2. Preserve the normal IR level stack protector check for platforms like
     OpenBSD for which we support platform specific stack protector
     generation.

The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:

  1. The decision on whether or not to perform a sibling call on certain
     platforms (for instance i386) requires lower level information
     related to available registers that can not be known at the IR level.

  2. Even if the previous point were not true, the decision on whether to
     perform a tail call is done in LowerCallTo in SelectionDAG which
     occurs after the Stack Protector Pass. As a result, one would need to
     put the relevant callinst into the stack protector check success
     basic block (where the return inst is placed) and then move it back
     later at SelectionDAG/MI time before the stack protector check if the
     tail call optimization failed. The MI level option was nixed
     immediately since it would require platform specific pattern
     matching. The SelectionDAG level option was nixed because
     SelectionDAG only processes one IR level basic block at a time
     implying one could not create a DAG Combine to move the callinst.

To get around this problem a few things were realized:

  1. While one can not handle multiple IR level basic blocks at the
     SelectionDAG Level, one can generate multiple machine basic blocks
     for one IR level basic block. This is how we handle bit tests and
     switches.

  2. At the MI level, tail calls are represented via a special return
     MIInst called "tcreturn". Thus if we know the basic block in which we
     wish to insert the stack protector check, we get the correct behavior
     by always inserting the stack protector check right before the return
     statement. This is a "magical transformation" since no matter where
     the stack protector check intrinsic is, we always insert the stack
     protector check code at the end of the BB.

Given the aforementioned constraints, the following solution was devised:

  1. On platforms that do not support SelectionDAG stack protector check
     generation, allow for the normal IR level stack protector check
     generation to continue.

  2. On platforms that do support SelectionDAG stack protector check
     generation:

    a. Use the IR level stack protector pass to decide if a stack
       protector is required/which BB we insert the stack protector check
       in by reusing the logic already therein. If we wish to generate a
       stack protector check in a basic block, we place a special IR
       intrinsic called llvm.stackprotectorcheck right before the BB's
       returninst or if there is a callinst that could potentially be
       sibling call optimized, before the call inst.

    b. Then when a BB with said intrinsic is processed, we codegen the BB
       normally via SelectBasicBlock. In said process, when we visit the
       stack protector check, we do not actually emit anything into the
       BB. Instead, we just initialize the stack protector descriptor
       class (which involves stashing information/creating the success
       mbbb and the failure mbb if we have not created one for this
       function yet) and export the guard variable that we are going to
       compare.

    c. After we finish selecting the basic block, in FinishBasicBlock if
       the StackProtectorDescriptor attached to the SelectionDAGBuilder is
       initialized, we first find a splice point in the parent basic block
       before the terminator and then splice the terminator of said basic
       block into the success basic block. Then we code-gen a new tail for
       the parent basic block consisting of the two loads, the comparison,
       and finally two branches to the success/failure basic blocks. We
       conclude by code-gening the failure basic block if we have not
       code-gened it already (all stack protector checks we generate in
       the same function, use the same failure basic block).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 07:00:16 +00:00
Craig Topper
1299e49ba7 Fix formatting. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 05:23:59 +00:00
Craig Topper
3b7722cf3a Add AVX-512 and related features to the CPUID detection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 05:22:42 +00:00
Craig Topper
b5e1d5b46f Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 04:24:14 +00:00