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2706 Commits

Author SHA1 Message Date
Evan Cheng
ed2ae136d2 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:40:23 +00:00
Evan Cheng
dca653951c Remove early IT block formation. It's not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 21:07:09 +00:00
Bob Wilson
e45f72c833 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so 
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 17:23:44 +00:00
Bob Wilson
b5b5057a70 ARM function alignments were off by a power of two. svn 83242 changed 
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 22:26:26 +00:00
Bob Wilson
21773e716f Add support for encoding VDUP (ARM core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:13:29 +00:00
Bob Wilson
d5a563de07 Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:34:07 +00:00
Jim Grosbach
077f1bfa91 skip dbg_value instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:55:24 +00:00
Bob Wilson
1ab38469df The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add 
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:25:11 +00:00
Rafael Espindola
d31f972bd3 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses 
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 14:02:34 +00:00
Duncan Sands
31a3a3ebaf Remove pointless variable LastDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:23:22 +00:00
Duncan Sands
58c86910b3 Remove unused variable Loc and pointless variables unified_syntax 
and thumb_mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:04:35 +00:00
Duncan Sands
978189e090 Remove an unused and a pointless variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:00:29 +00:00
Duncan Sands
90c64f4aac Remove initialized but otherwise unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 11:22:26 +00:00
Evan Cheng
c36b5b9730 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:38:36 +00:00
Evan Cheng
c170f66742 Change if-cvt options to something that actually as useable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:37:59 +00:00
Jakob Stoklund Olesen
628a79771b When no memoperands are present, assume unaligned, volatile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:13:07 +00:00
Bob Wilson
5cdede43e9 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92 Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 22:23:17 +00:00
Jim Grosbach
e89c5e57cc tidy up style. no functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:29:17 +00:00
Bob Wilson
08baddbc07 Refactor encoding function for NEON 1-register with modified immediate format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7 Support Thumb mode encoding of NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:12:19 +00:00
Jim Grosbach
e9e3f20ffb minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 04:27:01 +00:00
Eli Friedman
a2c6f457a4 Followup to r106770: actually generate SXTB and SXTH for sign-extensions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:36:50 +00:00
Bob Wilson
52e4a0a074 Add support for encoding NEON VMOV (from scalar to core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:07:15 +00:00
Evan Cheng
f6799394d5 It's now possible to run code placement pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 01:52:05 +00:00
Bob Wilson
80d9bc0336 Renumber NEON instruction formats to be consecutive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:05:09 +00:00
Bob Wilson
184723d9be Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to 
"N..." instead of "NEON..." for consistency with the other NEON format names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:56:05 +00:00
Bob Wilson
2653263165 Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. 
Renumber MiscFrm to 25.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:45:37 +00:00
Daniel Dunbar
e39e06af38 Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was 
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:14:54 +00:00
Evan Cheng
13151432ed Change if-conversion block size limit checks to add some flexibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:42:03 +00:00
Bob Wilson
5e7b607f72 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:40:46 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:55:36 +00:00
Bob Wilson
583a2a0615 Add support for encoding 2-register NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:17:19 +00:00
Bob Wilson
8c605c601d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:54:44 +00:00
Jim Grosbach
57bb394803 IT instructions are considered to be scheduling hazards, but are scheduled 
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:43:14 +00:00
Bob Wilson
ade57fa619 Add missing ARM and Thumb data layout info for vector types. 
Radar 8128745.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a Reduce indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:12:31 +00:00
Evan Cheng
8acf67672b Oops. IT block formation pass needs to be run at any optimization level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f PR7458: Try commuting Thumb2 instruction operands to put them into 2-address 
form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 16:50:20 +00:00
Bill Wendling
4b722108e2 We are missing opportunites to use ldm. Take code like this: 
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 23:00:16 +00:00
Dale Johannesen
e39fdbe118 Do not do tail calls to external symbols. If the 
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 18:52:34 +00:00
Jim Grosbach
5def57aaf4 When using libcall expansions for the atomic intrinsics, the explicit 
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 16:08:49 +00:00
Bob Wilson
a3a204664d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. 
Radar 8031193.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:04:24 +00:00
Dan Gohman
fe60104ac9 Use pre-increment instead of post-increment when the result is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 01:18:16 +00:00
Bob Wilson
56a1a69a35 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. 
Radar 8104310.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:27 +00:00
Evan Cheng
d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:14 +00:00
Dale Johannesen
b0ccb757b3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:49 +00:00