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2074 Commits

Author SHA1 Message Date
Bill Wendling
5f5bf3a3fd PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this 
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:49:02 +00:00
Dan Gohman
9ed06db5c8 Add support for lowering 128-bit shifts on ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:36:53 +00:00
Dale Johannesen
8419dd6aa6 Next bits of PPC byval handling. Basically functional 
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48028 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:27:40 +00:00
Chris Lattner
af8ee84fe5 Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:18:24 +00:00
Chris Lattner
49bd37d369 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 
with 32 or 64-bit operands/results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:13:51 +00:00
Dale Johannesen
1f797a32fd Next bit of PPC ByVal handling; call-site code seems 
correct now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47978 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-05 23:31:27 +00:00
Bill Wendling
2b5fab67c1 Removed spurious EnablePPCRS check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47918 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:27:33 +00:00
Dale Johannesen
5b3b695c2f Move PPC lowering functions into PPCTargetLowering 
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47917 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:17:14 +00:00
Bill Wendling
880d0f6018 Use a command-line option to turn register scavenging on/off for PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-04 23:13:51 +00:00
Bill Wendling
7194aaf738 This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-03 22:19:16 +00:00
Chris Lattner
150943c178 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47830 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 19:27:34 +00:00
Chris Lattner
3be4893dce Evan implemented this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47827 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-02 17:56:29 +00:00
Anton Korobeynikov
8213f9cf94 Use enumeration for preffered EH dwarf encoding reason 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47770 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 22:09:08 +00:00
Dale Johannesen
28d08fdb9f Interface of getByValTypeAlignment differed between 
generic & x86 versions; change generic to follow x86
and improve comments.  Add PPC version (not right
for non-Darwin.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 22:31:51 +00:00
Evan Cheng
fb8075d03f Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 00:43:03 +00:00
Anton Korobeynikov
7b1b7f5c5a EHPreferredDataFormat hook for PPC targets. Looks like Darwin 
uses the same encoding everywhere. Linux FIXME'ed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47701 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 23:49:15 +00:00
Dan Gohman
ec59b95a19 Don't hard-code the mask size to be 32, which is incorrect on ppc64 
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47692 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 21:12:32 +00:00
Bill Wendling
6ef781f3ce Final de-tabification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 06:33:05 +00:00
Dan Gohman
b3564aa836 Convert the last remaining users of the non-APInt form of 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 01:23:58 +00:00
Bill Wendling
e6d088acc9 Rename PrintableName to Name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:47:57 +00:00
Bill Wendling
74ab84c31e Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 
would have been a Godsend here!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:11:01 +00:00
Bill Wendling
181eb737b2 Some platforms use the same name for 32-bit and 64-bit registers (like 
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-24 00:56:13 +00:00
Anton Korobeynikov
7c1c261272 Remove bunch of gcc 4.3-related warnings from Target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-20 11:22:39 +00:00
Andrew Lenharth
d497d9fab6 I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-16 14:46:26 +00:00
Chris Lattner
ec321b4d64 Handle \n's in value names for more targets. The asm printers 
really really really need refactoring :(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47171 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-15 19:04:54 +00:00
Dale Johannesen
3b407444c9 Cosmetics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47168 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-15 18:40:53 +00:00
Dale Johannesen
ab1a0354ec Remove warning about 64-bit code on processor 
that doesn't support it.  Per Chris.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47162 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-15 18:09:51 +00:00
Dale Johannesen
db01c8ba26 Rewrite tblgen handling of subtarget features so 
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-14 23:35:16 +00:00
Nate Begeman
e179584f9b Change how FP immediates are handled. 
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-14 08:57:00 +00:00
Dan Gohman
977a76fbb6 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits 
to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 22:28:48 +00:00
Nicolas Geoffray
afe6c2b001 Enable exception handling int JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47079 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 18:39:37 +00:00
Chris Lattner
a1998d1cba Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47067 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 17:24:14 +00:00
Chris Lattner
9f72d1a730 don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. 
DAGCombine is now quite good at zapifying them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 07:35:30 +00:00
Nate Begeman
b5041b3085 readme updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47051 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 07:06:12 +00:00
Nate Begeman
ba8d51c1d7 Make register scavenging happy by not using a reg (CR0) that isn't defined 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 02:58:33 +00:00
Evan Cheng
a4d16a1f0d commuteInstr() can now commute non-ssa machine instrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 02:46:49 +00:00
Dan Gohman
fd29e0eb06 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. 
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 00:35:47 +00:00
Evan Cheng
394d28048c Revert r46916 PPCTargetAsmInfo.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47020 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-12 19:25:12 +00:00
Nate Begeman
a6ed0aa8ec additional missing feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46948 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-11 04:16:09 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-10 18:45:23 +00:00
Nick Lewycky
16b0bd6c83 Match GCC's behaviour for these sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46916 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-10 00:03:54 +00:00
Evan Cheng
5fd79d0560 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-08 21:20:40 +00:00
Dan Gohman
3069b87437 Follow Chris' suggestion; change the PseudoSourceValue accessors 
to return pointers instead of references, since this is always what
is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46857 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-07 18:41:25 +00:00
Dan Gohman
69de1932b3 Re-apply the memory operand changes, with a fix for the static 
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-06 22:27:42 +00:00
Nate Begeman
5a804e3e21 Ident mnemonics appropriately 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-05 08:49:09 +00:00
Evan Cheng
4e3f5a4e9c Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-04 23:06:48 +00:00
Evan Cheng
4eecdeb3fa Get rid of the annoying blank lines before labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-02 08:39:46 +00:00
Evan Cheng
fcf5d4f456 Unbreak ppc debug support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46665 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-02 05:06:29 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. 
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-02 04:07:54 +00:00
Evan Cheng
1b08bbca55 Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46635 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-01 09:10:45 +00:00