Commit Graph

14363 Commits

Author SHA1 Message Date
Eric Christopher
c4639d6ec2 Remove a function argument and propagate const around accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 22:42:15 +00:00
Eric Christopher
0f1c7f6216 Whitespace and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 22:42:10 +00:00
Anton Korobeynikov
239938ff77 Make AsmPrinter::EmitTTypeReference() more robust - put
the zero GV check inside, so we won't forget it at the caller side.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 21:17:20 +00:00
Anton Korobeynikov
2386fc8daa Factor out type info emission into separate routine.
It turned out that ARM wants different layout of type infos.
This is yet another patch in attempt to fix PR7187 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168325 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 21:06:26 +00:00
Eric Christopher
97c3472bf9 Move section label emission to module end. Nothing should be
depending on them being emitted before the text and/or data
sections and testing didn't uncover any.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 19:43:59 +00:00
Jakob Stoklund Olesen
e42561ad0c Handle mixed normal and early-clobber defs on inline asm.
PR14376.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 19:31:10 +00:00
Craig Topper
8f54a53f0e Move else onto line with preceding closing brace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19 00:11:50 +00:00
Andrew Trick
e1f663933a Broaden isSchedulingBoundary to check aliases of SP.
On PPC the stack pointer is X1, but ADJCALLSTACK writes R1.

Fixes PR14315: Register regmask dependency problem with misched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17 03:35:11 +00:00
Eli Friedman
43147afd71 Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17 01:52:46 +00:00
Andrew Trick
cdf493dd0b Use array_pod_sort instead of std::sort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:33:38 +00:00
Craig Topper
08ac4691c6 Remove conditions from 'else if' that were guaranteed by preceding 'if'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 20:01:39 +00:00
Craig Topper
df0ea8dcad Factor out the final FADD that's common to multiple code paths in the visitLog* functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 19:08:44 +00:00
Craig Topper
9bd4dd742e Factor some common code to reduce compile size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 07:48:23 +00:00
Eli Friedman
846ce8ea67 Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 22:44:27 +00:00
Ulrich Weigand
f38aa4272c Use std::stable_sort instead of std::sort when sorting stack slots
to guarantee deterministic code generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 19:33:30 +00:00
Chad Rosier
4823be3be1 [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a false
positive.

In this particular case, R6 was being spilled by the register scavenger when it
was in fact dead.  The isUsed function reported R6 as used because the R6_R7
alias was reserved (due to the fact that we've reserved R7 as the FP).  The
solution is to only check if the original register (i.e., R6) isReserved and
not the aliases.  The aliases are only checked to make sure they're available.

The test case is derived from one of the nightly tester benchmarks and is rather
intractable and difficult to reproduce, so I haven't included it.
rdar://12592448


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 18:13:20 +00:00
Sergei Larin
009cf9e9a3 Fix indeterminism in MI scheduler DAG construction.
Similarly to several recent fixes throughout the code replace std::map use with the MapVector.
Add find() method to the MapVector.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 17:45:50 +00:00
Craig Topper
490104720d Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 06:51:10 +00:00
Andrew Trick
c6d6aeb95f Fix an obvious merge bug in -join-globalcopies (disabled).
Jakub Staszak spotted this in review. I don't notice these things
until I manually rerun benchmarks. But reducing unit tests is a very
high priority.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 02:32:22 +00:00
Jakub Staszak
8762a6bc2b Use reserve() to avoid vector reallocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 22:42:17 +00:00
Jakub Staszak
39c71da6db canJoinPhys method doesn't modify CoalescerPair. Make it const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:31:04 +00:00
Chad Rosier
984639b7a4 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 20:25:37 +00:00
Anton Korobeynikov
062a6c8380 Fix really stupid ARM EHABI info generation bug: we should not emit
eh table and handler data if there are no landing pads in the function.
Patch by Logan Chien with some cleanups from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 19:13:30 +00:00
Craig Topper
32631d1a5a Add newlines to end of debug messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 05:20:09 +00:00
Rafael Espindola
8e2b8ae3b1 Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 05:08:56 +00:00
Anton Korobeynikov
25efd6d556 Use TARGET2 relocation for TType references on ARM.
Do some cleanup of the code while here.

Inspired by patch by Logan Chien!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14 01:47:00 +00:00
Eric Christopher
242343d1ab Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."
temporarily as it is breaking the gdb bots.

This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 23:30:43 +00:00
Andrew Trick
a6aae0273a Revert -join-splitedges to a boolean cmd line option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 22:19:48 +00:00
Andrew Trick
3106aa125e The MachineScheduler does not currently require JoinSplitEdges.
This option will eventually either be enabled unconditionally or
replaced by a more general live range splitting optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 22:15:40 +00:00
Michael J. Spencer
4de5872ded [MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 22:04:09 +00:00
Ulrich Weigand
b64e2115de Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 18:40:58 +00:00
Andrew Trick
2344abc939 Fix -join-splitedges: my previous "cleanup" broke it.
Working on reducing unit tests.
This won't be enabled unless a subtarget enables misched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 17:37:46 +00:00
Duncan Sands
b2df01ab2a Codegen support for arbitrary vector getelementptrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 13:01:58 +00:00
Andrew Trick
ad1cc1d1bf misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 08:47:29 +00:00
Andrew Trick
265058d923 Added RegisterCoalescer support for joining global copies first.
This adds the -join-globalcopies option which can be enabled by
default once misched is also enabled.

Ideally, the register coalescer would be able to split local live
ranges in a way that produces copies that can be easily resolved by
the scheduler. Until then, this heuristic should be good enough to at
least allow the scheduler to run after coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 08:47:25 +00:00
Andrew Trick
cf6b6131dd misched: Don't consider artificial edges weak edges.
For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 02:35:06 +00:00
Bill Wendling
e7ff4c14b1 Use the 'count' attribute instead of the 'upper_bound' attribute.
If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the
same for both of them because we use the 'upper_bound' attribute. Instead use
the 'count' attrbute, which gives the correct number of elements in the array.
<rdar://problem/12566646>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 02:31:47 +00:00
Andrew Trick
f546ac5f9b Cleanup the main RegisterCoalescer loop.
Block priorities still apply outside loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 00:34:44 +00:00
Andrew Trick
43736c7cfa Cleanup -join-splitedges. Make the loop more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 23:59:48 +00:00
Eric Christopher
f5b6dcd392 Add an option to enable prototype "fission" capabilities and debug changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 22:22:20 +00:00
Andrew Trick
3c9e55867e Added a temporary option to avoid critical edges splitting.
This teaches the register coalescer to be less prone to split critical
edges. I am currently benchmarking this with the new (post-coalescer)
scheduler. I plan to enable this by default and remove the option as
soon as misched is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 21:42:40 +00:00
Andrew Trick
a7d2d564d9 misched: rename interfaceto avoid gcc warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 21:28:10 +00:00
Andrew Trick
6996fd0b54 misched: Target-independent support for MacroFusion.
Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.

Next step: target hook implementations with test cases, and enable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 19:52:20 +00:00
Andrew Trick
9b5caaa9c4 misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 19:40:10 +00:00
Andrew Trick
ae692f2bae misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12 19:28:57 +00:00
Jakob Stoklund Olesen
722c9a7925 Fix assertions in updateRegMaskSlots().
The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B'
slots. This broke the checks in the assertions.

This fixes PR14302.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 19:18:49 +00:00
Benjamin Kramer
b754687fd7 Silence GCC warning about falling off the end of a non-void function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 15:45:22 +00:00
Andrew Trick
3b87f6204f misched: Heuristics based on the machine model.
misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 07:05:09 +00:00
Andrew Trick
881a05b46c misched: handle on-the-fly regpressure queries better for 2-addr
instructions without relying on liveintervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 07:05:05 +00:00
Bill Wendling
168c190c58 Add comment describing what's going on here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 05:19:04 +00:00