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Author SHA1 Message Date
Andrew Trick
8ceaa660bf Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:18:18 +00:00
Andrew Trick
acddd4963d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:18:15 +00:00
Andrew Trick
084e179f09 Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:18:12 +00:00
Andrew Trick
e75537a243 misched comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:18:08 +00:00
Andrew Trick
6cfb14f6df misched: Use the StartBlock/FinishBlock hooks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:18:05 +00:00
Eric Christopher
8938895a83 Add the DW_AT_APPLE_runtime_class attribute to forward declarations 
as well as completely defined classes.

This fixes rdar://10956070

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152171 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:15:19 +00:00
Evan Cheng
03be3622aa Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 23:33:32 +00:00
Jim Grosbach
4d0983a4d7 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 23:10:38 +00:00
Jakob Stoklund Olesen
c511c2827d Hoist common code out of if statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152153 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 22:27:13 +00:00
Jim Grosbach
c0fc450f07 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 22:01:44 +00:00
Owen Anderson
40530ad3a8 Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 21:48:32 +00:00
Benjamin Kramer
2945a32ffd SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap. 
This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 20:40:02 +00:00
Eli Friedman
54427e5219 Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 19:58:46 +00:00
Ted Kremenek
f0a68131de Add new load commands for MachO. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152135 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 19:54:44 +00:00
Daniel Dunbar
956690508c build/Darwin: Make it easy to cause all tools to get codesigned (with make CODESIGN_TOOLS=1). 
- On OS X 10.7+ this is apparently recommended practice. This maybe should
   become a configurey thing one day, but I'm not sure it is right to
   automatically turn it on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152133 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 19:07:38 +00:00
Jim Grosbach
bde1b2a5a8 Tidy up. Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen
14f87e01ca Allow the same types in DPair as in QPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:44:11 +00:00
Kevin Enderby
158c8a49c2 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:33:12 +00:00
Roman Divacky
e46137f498 Convert PowerPC to register mask operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 16:41:49 +00:00
Benjamin Kramer
e6f1355c38 Remove excess const, a const_iterator shouldn't be const itself. 
Fixes 1242 warnings from gcc during clang build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152120 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 13:32:36 +00:00
Jay Foad
4e3e5dec1a Change ConstantAggrUniqueMap to use Chandler's new hashing 
implementation. Patch by Meador Inge

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152116 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 10:43:52 +00:00
Bill Wendling
b3ef2230ff Add column width. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152115 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 09:23:25 +00:00
Bill Wendling
cf1f6c8a37 Remove short tag marker. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152114 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 09:22:03 +00:00
Bill Wendling
63f5a1f4d6 Appease the HTML validation gods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152113 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 09:20:59 +00:00
Bill Wendling
0eb5914411 Fix validation errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 09:17:39 +00:00
Bill Wendling
a0edecf191 Fix validation errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152111 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 09:17:04 +00:00
Bill Wendling
88a6808377 Add missing end tags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 08:59:13 +00:00
Argyrios Kyrtzidis
bb07f21c76 [TinyPtrVector] Add erase method and const-goodness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 07:14:58 +00:00
Argyrios Kyrtzidis
0db235a2b0 PointerUnion::getAddrOf() does not need to be template since we can only 
use the first pointer type for it. Rename it to getAddrOfPtr1().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 07:14:54 +00:00
Craig Topper
f0c094b115 Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 06:04:39 +00:00
Craig Topper
904a01820c Add asserts to ensure that values will fit into the tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 04:39:52 +00:00
Craig Topper
aff18aee56 Increase number of allowed registers in register classes to 64k instead of 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152100 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 03:44:22 +00:00
Craig Topper
696f5ab12e Revert r152016 and allow overlap, sub, super register tables to be more than 64k entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152099 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 03:28:45 +00:00
Argyrios Kyrtzidis
e196633cfd Remove UsuallyTinyPtrVector. 
It is just a worse version of TinyPtrVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 03:02:16 +00:00
Jakob Stoklund Olesen
3247af2949 Add <imp-def> operands when reloading into physregs. 
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:48:17 +00:00
Eric Christopher
5b7634fd74 Fix up link and a couple small edits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152094 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:25:41 +00:00
Eric Christopher
25e6329e68 Add the beginnings of documentation for the Name Accelerator Tables. 
Based on a writeup originally by Greg Clayton.

Abuse div and pre tags horribly. Needs a bit more cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:25:38 +00:00
Eric Christopher
fc7243a1f6 Delete trailing whitespace to clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:25:36 +00:00
Argyrios Kyrtzidis
bae75596ae Add include/llvm/ADT/UsuallyTinyPtrVector.h which is a vector that 
optimizes the case where there is only one element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:08:48 +00:00
Evan Cheng
8250d7385a Avoid finalizeBundles infinite looping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:00:52 +00:00
Owen Anderson
afd3d56b9d Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 00:29:31 +00:00
Lang Hames
4f92b5e616 Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 00:19:55 +00:00
Eli Friedman
923bb4117a A few more cases of missing masking in ComputeMaskedBits; found by inspection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152070 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:22:40 +00:00
Jim Grosbach
bc978a60d9 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:16:31 +00:00
Jim Grosbach
7cc0426489 Nuke a bit of dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:09:51 +00:00
Eli Friedman
049d08f5c9 Make sure we don't return bits outside the mask in ComputeMaskedBits. PR12189. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152066 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:09:40 +00:00
Jim Grosbach
c3384c93c0 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 21:43:40 +00:00
Jim Grosbach
af9f4bc752 ARM Remove a bit of dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 21:09:58 +00:00
Jim Grosbach
28f08c93e7 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:30 +00:00
Jim Grosbach
33ca87affb MCRegisterInfo-ize getMatchingSuperReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:24 +00:00