Preston Gurd
deaa3f3e52
Added X86 Atom latencies for instructions in X86InstrInfo.td.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:58:35 +00:00
Eric Christopher
05b7a50210
Add support for the 'X' inline asm operand modifier.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:48:22 +00:00
Sirish Pande
0cfb5cfe97
Hexagon V5 Support - V5 td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:24:28 +00:00
Sirish Pande
7517bbc91a
Hexagon V5 FP Support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:20:25 +00:00
Manman Ren
fe65d98dad
Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
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This commit broke an external linux bot and gave a compile-time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 18:49:43 +00:00
Manman Ren
8ae4f062e4
ARM: peephole optimization to remove cmp instruction
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This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 16:48:21 +00:00
Nadav Rotem
b88e8dd31d
Fix merge-typo and cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:50:02 +00:00
Nadav Rotem
b210651654
AVX2: Add an additional broadcast idiom.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:39:13 +00:00
Nadav Rotem
5fc2187a02
Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program.
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Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.
Fix PR11900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:22:05 +00:00
Roman Divacky
d9b41b339d
Mark .opd @progbits, thus avoiding a warning from asm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 18:24:23 +00:00
Akira Hatanaka
2b409b65d4
Add another peephole pattern for conditional moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 02:29:29 +00:00
Jakob Stoklund Olesen
cf661a040c
Use ptr_rc_tailcall instead of GR32_TC.
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The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 01:50:09 +00:00
Akira Hatanaka
56ec9f2c09
Make register FP allocatable if the compiled function does not have dynamic
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allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 01:38:13 +00:00
Akira Hatanaka
a284acb8a7
Expand 64-bit shifts if target ABI is O32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 00:55:21 +00:00
Richard Trieu
220ee59b90
Remove unused variable to silence compiler warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 00:30:21 +00:00
Jakob Stoklund Olesen
f191b43103
Use a shared function for a common operation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156441 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 23:27:30 +00:00
Eric Christopher
22b291abd8
Remove excess semi-colons to quiet warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 20:45:04 +00:00
Sirish Pande
ab3a7fb244
Update load/store instruction patterns in Hexagon V4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 19:50:20 +00:00
Akira Hatanaka
e10d9722cd
Define mips16 instruction formats.
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Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 19:08:58 +00:00
Jakob Stoklund Olesen
1910cb1e3d
s/CSR_Ghc/CSR_NoRegs/
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Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 15:07:29 +00:00
Craig Topper
189bce48c7
Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156375 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 06:58:15 +00:00
Jakob Stoklund Olesen
397fc4874e
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
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The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
9b23d57dc4
Fix bug in TRI::getCommonSuperRegClass().
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Test cases for this code are coming. It is not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 21:59:31 +00:00
Jakob Stoklund Olesen
fd87839a48
Add TRI::getCommonSuperRegClass().
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This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:
PreA
SuperRC ----------> RCA
| |
| |
PreB | | SubA
| |
| |
V V
RCB ----------> SubRC
SubB
This can be used to coalesce copies like:
%vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156317 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 19:14:58 +00:00
Chad Rosier
42726835e3
Fix a regression from r147481. This combine should only happen if there is a
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single use.
rdar://11360370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 18:47:44 +00:00
Manman Ren
ed57984483
X86: optimization for -(x != 0)
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This patch will optimize -(x != 0) on X86
FROM
cmpl $0x01,%edi
sbbl %eax,%eax
notl %eax
TO
negl %edi
sbbl %eax %eax
In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
rdar: 10961709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 18:06:23 +00:00
Eric Christopher
af97f73ca0
Add support for the 'x' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 06:25:19 +00:00
Eric Christopher
4adbefebd2
Add support for the 'l' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 06:25:15 +00:00
Eric Christopher
1d5a392e2c
Add support for the 'c' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 06:25:10 +00:00
Eric Christopher
54412a789a
Add support for the 'P' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 06:25:02 +00:00
Craig Topper
ef2b8bda02
Fix some issues in the f16c instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 06:00:15 +00:00
Eric Christopher
1ce2034e43
Add support for the 'O' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:46:48 +00:00
Eric Christopher
60cfc7908e
Add support for the 'N' inline asm constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:46:43 +00:00
Eric Christopher
5ac47bba83
Add support for the 'L' inline asm constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:46:37 +00:00
Eric Christopher
f49f846eec
Add support for the inline asm constraint 'K'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:46:29 +00:00
Craig Topper
5f9cccc509
Add SSE4A MOVNTSS/MOVNTSD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:36:19 +00:00
Eric Christopher
e5076d484b
Support the 'J' constraint.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:42 +00:00
Eric Christopher
50ab03954e
Add support for the 'I' inline asm constraint. Also add tests
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from the previous 2 patches.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:32 +00:00
Eric Christopher
0ed1f764f4
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
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Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:22 +00:00
Eric Christopher
3ccbd47ecb
When using inline asm constraints representing
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non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 03:13:16 +00:00
Craig Topper
d978c54e60
Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 19:46:21 +00:00
Craig Topper
bdcbcb3ae7
Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:54:26 +00:00
Craig Topper
156f5bb56e
Add shuffle decode support for VPERMQ/VPERMPD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:44:02 +00:00
Jim Grosbach
e5f31ad55e
Nuke a few dead remnants of the CBE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 17:45:12 +00:00
Benjamin Kramer
aaf723dd2b
Add a new target hook "predictableSelectIsExpensive".
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This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 12:49:14 +00:00
Benjamin Kramer
af87831519
NVPTX: Initialize the UseF32FTZ flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 11:22:02 +00:00
Eric Christopher
f2eed387d4
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 01:16:06 +00:00
David Blaikie
03ba93e194
Fix warnings in release build.
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This fixes a couple of Clang warnings in release builds of LLVM:
* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:34:16 +00:00
Kevin Enderby
3610a15c35
Tweak to the fix in r156212, as with the change in removing the shift the
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SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:09:52 +00:00
Kevin Enderby
ce734d5ffe
Fix a bug in the ARM disassembler for wide branch conditional instructions
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where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:02:27 +00:00