Commit Graph

20603 Commits

Author SHA1 Message Date
Joerg Sonnenberger
66b7139b1b Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 20:23:19 +00:00
Joey Gouly
0b90c6223d [ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 17:38:16 +00:00
Elena Demikhovsky
d371d4f0f4 AVX-512: added conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 13:54:04 +00:00
Tim Northover
5d8c2e460c DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 13:46:45 +00:00
Joey Gouly
dcfa0f7a40 [ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 11:24:16 +00:00
Tim Northover
c59efb626a ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 10:31:36 +00:00
Michel Danzer
845ad06efb R600/SI: Enable local-memory-two-objects lit test
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 10:28:26 +00:00
Daniel Sanders
bc4e0586bd [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v when non-byte vectors are used.
Note that all of these tests use ld.b and st.b for the loads and stores
regardless of the data size. This is because the definition of bitcast is
equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts
to/from v16i8 into the load/store nodes to product load/store nodes with
type v16i8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189333 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 10:16:17 +00:00
Daniel Sanders
62f61bf907 [mips][msa] Added spill/reload support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 10:04:21 +00:00
Richard Sandiford
842a1be06c [SystemZ] Extend memcpy and memset support to all constant lengths
Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs.
Lengths above that threshold use a loop to handle X*256 bytes followed
by a single MVC to handle the excess (if any).  This loop will also be
needed in future when support for variable lengths is added.

Because the same tablegen classes are used to define MVC and CLC,
the patch also has the side-effect of defining a pseudo loop instruction
for CLC.  That instruction isn't used yet (and wouldn't be handled correctly
if it were).  I'm planning to use it soon though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 09:54:29 +00:00
Daniel Sanders
c9617b9a9d [mips][msa] Added bitconverts for vector types for big and little-endian
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 09:40:30 +00:00
Elena Demikhovsky
1567abe74f AVX-512: Added FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 08:39:25 +00:00
Kai Nacke
f0a0d57808 Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s

Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189309 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 04:16:16 +00:00
Eric Christopher
bf6f1f2a32 Add derived from source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189301 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 00:46:28 +00:00
Eric Christopher
478a1189cb Add a testcase to ensure that the pubnames section uses an offset
off of the debug_info section even when split dwarf is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 00:36:19 +00:00
Matt Arsenault
e3e5f77d77 Fix lint assert on integer vector division
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 23:29:33 +00:00
Eric Christopher
63ae7c9aec Treat the pubtypes section similarly to the pubnames section and emit
it by default under linux or when we're trying to keep compatibility
with old gdb versions.

Fix testcase for option name change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189289 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 23:24:35 +00:00
Matt Arsenault
4b272493b7 Fix inserting instructions before last in bundle.
The builder inserts from before the insert point,
not after, so this would insert before the last
instruction in the bundle instead of after it.

I'm not sure if this can actually be a problem
with any of the current insertions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 23:08:37 +00:00
Manman Ren
6e3cd0ebe2 Debug Info: add an identifier field to DICompositeType.
DICompositeType will have an identifier field at position 14. For now, the
field is set to null in DIBuilder.
For DICompositeTypes where the template argument field (the 13th field)
was optional, modify DIBuilder to make sure the template argument field is set.
Now DICompositeType has 15 fields.

Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode.
Update verifier to check that DICompositeType has 15 fields and the last
field is null or a MDString.

Update testing cases to include an extra field for DICompositeType.
The identifier field will be used by type uniquing so a front end can
genearte a DICompositeType with a unique identifer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 22:39:55 +00:00
Nadav Rotem
4bf6326d08 LoopVectorize: Implement partial loop unrolling when vectorization is not profitable.
This patch enables unrolling of loops when vectorization is legal but not profitable.
We add a new class InnerLoopUnroller, that extends InnerLoopVectorizer and replaces some of the vector-specific logic with scalars.

This patch does not introduce any runtime regressions and improves the following workloads:

SingleSource/Benchmarks/Shootout/matrix -22.64%
SingleSource/Benchmarks/Shootout-C++/matrix -13.06%
External/SPEC/CINT2006/464_h264ref/464_h264ref  -3.99%
SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding -1.95%



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 22:33:26 +00:00
Jim Grosbach
19dc6e6736 ARM: Enable machine verifier for a few more tests.
Now that fast-isel is in better shape, we can enable the machine
verifier for these tests, too.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 20:22:08 +00:00
Jim Grosbach
383a810b12 ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 20:22:05 +00:00
Jim Grosbach
e3dad19e0d ARM: FastISel verifier error cleanup.
Constant pool and global value reference instructions need more
restricted register classes than plain GPR.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 20:07:29 +00:00
Bill Schmidt
055d207426 [PowerPC] More fast-isel chunks (returns and integer extends)
Incremental improvement to fast-isel for PPC64.  This allows us to
select on ret, sext, and zext.  Filling in sext/zext improves some of
the existing logic in handling compare-immediates that needed extends.

A simplified return convention for fast-isel is also added to the
PPC64 calling conventions.  All call/return processing for DAG
selection is handled with custom code, so there isn't an existing CC
to rely on here.  The include of PPCGenCallingConv.inc causes compiler
warnings due to the 32-bit calling conventions that are not used, so
the dummy function "usePPC32CCs()" is added here to silence those.

Test cases for the return and extend logic are added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 19:42:51 +00:00
Matt Arsenault
3d59252450 Forgot to add slp threshold to test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 18:08:35 +00:00
Matt Arsenault
1b00d91005 Vectorize starting from insertelements building a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 17:56:35 +00:00
Tom Stellard
edd08f7428 SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()
If we have a binary operation like ISD:ADD, we can set the result type
equal to the result type of one of its operands rather than using
TargetLowering::getPointerTy().

Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary
operation can be replaced with:
DAG.getConstant(C, OtherOperand.getValueType());

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:06:10 +00:00
Tom Stellard
d08a930361 R600: Add support for vector local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:06:04 +00:00
Tom Stellard
a01cdea9c6 R600: Add support for i8 and i16 local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:59 +00:00
Tom Stellard
c52565157d SelectionDAG: Use correct pointer size when splitting vector stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:55 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:49 +00:00
Tom Stellard
7a0282daeb R600: Add support for v4i32 and v2i32 local stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:44 +00:00
Tom Stellard
da25cd3e6d SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:36 +00:00
Elena Demikhovsky
92bfb54770 AVX-512: Added shuffle instructions -
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 12:45:35 +00:00
Vladimir Medic
e4bf77a128 This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 10:02:40 +00:00
Bill Schmidt
3fad2bcd25 [PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code.  This handles direct
and indirect branches, as well as feeding compares for direct
branches.  PPCFastISel::PPCEmitIntExt() is just roughed in and will be
expanded in a future patch.  This also corrects a problem with
selection for constant pool entries in JIT mode or with small code
model.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 22:33:42 +00:00
Craig Topper
a4959f3f6e First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.

Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 22:23:38 +00:00
Venkatraman Govindaraju
2f17d0facf [Sparc] Add long double (f128) instructions to sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 18:30:06 +00:00
Venkatraman Govindaraju
5ec8afa7cf [Sparc] Added V9's extra floating point registers and their aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 17:03:02 +00:00
Elena Demikhovsky
41f7baf181 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 12:54:30 +00:00
Reed Kotler
5e5c3069cd Start to add the LLVM builtins to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted

Resubmit this patch. The target triple needs to be added to the test so that 
clang does not tell the backend the wrong target when the host is BSD. There
is a clang bug in here somewhere that I need to track down. At Mips this
has been filed internally as a bug.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 02:40:25 +00:00
Shuxin Yang
0570be8404 Revert 189161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 17:53:16 +00:00
Reed Kotler
cbbd1eeecb Start to add the builtind to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 01:24:44 +00:00
Justin Holewinski
30632d2fbb [NVPTX] Re-enable assembly printing support for inline assembly
This support was removed by accident during the MC conversion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 01:17:23 +00:00
Rafael Espindola
cb1339ebeb Update test to use rdrnd instead of rdrand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:49:02 +00:00
Rafael Espindola
9b14371830 Update tests to use sse4.2 instead of sse42.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:46:35 +00:00
Rafael Espindola
7cb1b5f5bf Replace more uses of sse41 with sse4.1.
llc using the host cpu features and *waning* on unknown features is probably
not a good thing :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:39:19 +00:00
Rafael Espindola
56afd5e90b Update a test that I missed in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:27:02 +00:00
Rafael Espindola
4aa8bdaa46 Rename features to match what gcc and clang use.
There is no advantage in being different and using the same names simplifies
clang a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:21:34 +00:00
Peter Collingbourne
f3c0314310 DataFlowSanitizer: correctly combine labels in the case where they are equal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 18:45:06 +00:00