Rafael Espindola
26c8dcc692
Always compute all the bits in ComputeMaskedBits.
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This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 12:51:34 +00:00
Craig Topper
769bbfd951
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 05:20:24 +00:00
Benjamin Kramer
c97ef618d2
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
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All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 08:32:38 +00:00
Craig Topper
7c0b3c1fb6
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 07:01:04 +00:00
Craig Topper
17463b3ef1
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 06:09:36 +00:00
Nadav Rotem
4ac9081c71
This commit contains a few changes that had to go in together.
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1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
(and also scalar_to_vector).
2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))
3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y).
4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.
Code which was previously compiled to this:
movd (%rsi), %xmm0
movdqa .LCPI0_0(%rip), %xmm2
pshufb %xmm2, %xmm0
movd (%rdi), %xmm1
pshufb %xmm2, %xmm1
pxor %xmm0, %xmm1
pshufb .LCPI0_1(%rip), %xmm1
movd %xmm1, (%rdi)
ret
Now compiles to this:
movl (%rsi), %eax
xorl %eax, (%rdi)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01 19:31:22 +00:00
Benjamin Kramer
cef670a3a3
Rip out emission of the regIsInRegClass function for the asm printer.
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It's slow, bloated and completely redundant with MCRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 23:13:40 +00:00
Benjamin Kramer
2f1abe9a5f
Add a note about a missed cmov -> sbb opportunity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 13:02:58 +00:00
Lang Hames
616c841946
Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 19:54:28 +00:00
Benjamin Kramer
73478404af
Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 12:37:26 +00:00
Craig Topper
9e6ddcb88e
Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 07:11:23 +00:00
Joel Jones
76d03106df
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
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This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 05:45:48 +00:00
Joel Jones
f75f4271f4
Reverted to revision 153616 to unblock build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 01:20:56 +00:00
Joel Jones
c367a3eb73
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
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This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 00:37:47 +00:00
Craig Topper
4e02f23de2
Prune some includes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:54:11 +00:00
Craig Topper
c89c744b69
Remove unnecessary llvm:: qualifications
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:21:54 +00:00
Joerg Sonnenberger
d9e85ef08b
Put Is64BitMemOperand into !defined(NDEBUG) for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 14:09:26 +00:00
Benjamin Kramer
47817f30f2
Use a signed value for this enum to avoid spuriuos warnings from gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 13:48:11 +00:00
Joerg Sonnenberger
4fd3d29275
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 05:48:07 +00:00
Craig Topper
3d092dbb91
Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 02:14:01 +00:00
Chad Rosier
1b1fdc0599
[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to
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vextractf128 with 128-bit mem dest.
Combines
vextractf128 $0, %ymm0, %xmm0
vmovaps %xmm0, (%rdi)
to
vextractf128 $0, %ymm0, (%rdi)
rdar://11082570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:43:40 +00:00
Chad Rosier
a3bfdf536e
[avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give
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precedence over the VINSERTF128 avx1 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:45:07 +00:00
Chad Rosier
666da1611a
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:38:33 +00:00
Chad Rosier
36a273a76c
[avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove
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whitespace from test case. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:24:55 +00:00
Chad Rosier
33e528d44d
[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
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This results in things such as
vmovups 16(%rdi), %xmm0
vinsertf128 $1, %xmm0, %ymm0, %ymm0
to be combined to
vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
rdar://11076953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:08:51 +00:00
Craig Topper
89f4e6639d
Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 07:17:59 +00:00
Craig Topper
a1ffc681ed
Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 06:42:26 +00:00
Preston Gurd
3e99b715d1
This patch adds X86 instruction itineraries for non-pseudo opcodes in
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X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 14:10:12 +00:00
Benjamin Kramer
8118c94a55
Add a note for -ffast-math optimization of vector norm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 00:43:34 +00:00
Craig Topper
97327dc6ef
isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-18 22:50:10 +00:00
Craig Topper
79aa3417eb
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
Chad Rosier
38ca0d78a2
[avx] Add patterns for VINSERTF128rm.
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This results in things such as
vmovaps -96(%rbx), %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
to be combined to
vinsertf128 $1, -96(%rbx), %ymm0, %ymm0
rdar://10643481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 00:45:30 +00:00
Kevin Enderby
0f5ab7c5f3
Change the X86 assembler to not require a segment register on string
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instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 19:47:55 +00:00
Kevin Enderby
84faf65912
Added a missing error check for X86 assembly with mismatched base and index
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registers not both being 64-bit or both being 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12 21:32:09 +00:00
Craig Topper
c5eaae4e9b
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11 07:57:25 +00:00
Kay Tiong Khoo
5a08cf4d34
*fix typo in comment; test of commit access
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 21:29:49 +00:00
Benjamin Kramer
63155f967c
C files in llvm still have to be C89 compliant, remove C++-style comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 15:10:06 +00:00
Bill Wendling
e060eb8916
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 07:37:27 +00:00
Kevin Enderby
58dfaa1465
Add the missing call to Error when a bad X86 scale expression is parsed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 22:24:10 +00:00
Kevin Enderby
faf72ffda3
Fix the x86 disassembler to at least print the lock prefix if it is the first
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 17:52:49 +00:00
Craig Topper
72051bf629
Use uint16_t to store opcodes in static tables in X86 backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 07:45:21 +00:00
Chad Rosier
abd6674166
Fix a regression from r147481.
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Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 02:00:48 +00:00
Eli Friedman
54427e5219
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 19:58:46 +00:00
Jim Grosbach
c6449b636f
Make MCRegisterInfo available to the the MCInstPrinter.
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Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:33:20 +00:00
Chad Rosier
c8d7eea264
Address Evan's comments for r151877.
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Specifically, remove the magic number when checking to see if the copy has a
glue operand and simplify the checking logic.
rdar://10930395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:27:12 +00:00
Eli Friedman
ec93b6deca
Make aliases for shld and shrd match gas. PR12173.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 04:31:54 +00:00
Craig Topper
e4fd907e72
Use uint16_t to store register overlaps to reduce static data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Craig Topper
015f228861
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 03:33:22 +00:00
Craig Topper
991271d9c4
Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 02:16:41 +00:00
Chad Rosier
74bab7f597
Prevent obscure and incorrect tail-call optimization.
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In this instance we are generating the tail-call during legalizeDAG. The 2nd
floor call can't be a tail call because it clobbers %xmm1, which is defined by
the first floor call. The first floor call can't be a tail-call because it's
not in the tail position. The only reasonable way I could think to fix this
in a target-independent manner was to check for glue logic on the copy reg.
rdar://10930395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02 02:50:46 +00:00