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290 Commits

Author SHA1 Message Date
Chandler Carruth
37886438dd Fix a memory leak in the hexagon scheduler. We call initialize here more 
than once, and the second time through we leaked memory. Found thanks to
the vg-leak bot, but I can't locally reproduce it with valgrind. The
debugger confirms that it is in fact leaking here.

This whole code is totally gross. Why is initialize being called on each
runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their
lifetimes better defined? Anyways, this is just a surgical change to
help out the leak checking bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187299 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-27 10:48:45 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-14 04:42:23 +00:00
Jakob Stoklund Olesen
f349a6e9e6 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 13:54:20 +00:00
Jakob Stoklund Olesen
c93822901a Revert r185595-185596 which broke buildbots. 
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen
62204220e1 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 23:56:31 +00:00
Benjamin Kramer
b0bbfaf3b3 Hexagon: Avoid unused variable warnings in Release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 17:24:00 +00:00
Richard Trieu
a785a7bf51 Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 23:06:23 +00:00
Richard Trieu
d1fe8d5212 Change assert(0 && "text") to llvm_unreachable(0 && "text") 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 23:46:19 +00:00
Richard Trieu
c09324483c Fix broken asserts that never fire. 
Change assert("text") to assert(0 && "text").  The first case is a const char *
to bool conversion, which always evaluates to true, never triggering the
assert.  The second case will always trigger the assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185227 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 21:54:25 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-22 18:37:38 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:36:55 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:27 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize. 
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:49:57 +00:00
Bill Wendling
54a56fad36 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:19:56 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:43:09 +00:00
Ahmed Bougacha
23ed37a6b7 Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-31 23:45:26 +00:00
Andrew Trick
6e0b2a0cb0 Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 22:03:55 +00:00
Jyotsna Verma
ee6e242e78 Hexagon: Typo fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-28 19:01:45 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:42:55 +00:00
Benjamin Kramer
a32218a7ec Hexagon: Make helper functions static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 15:43:11 +00:00
Jyotsna Verma
b4b14070a4 Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182390 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 15:54:32 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-18 00:21:46 +00:00
Benjamin Kramer
033f3b7eb6 Don't cast away constness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 11:39:41 +00:00
Rafael Espindola
992c3817ea Remove dead calls to addFrameMove. 
Without a PROLOG_LABEL present, the cfi instructions are never printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 15:08:37 +00:00
Jyotsna Verma
a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction 
where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 18:54:06 +00:00
Jyotsna Verma
36e1b51438 Hexagon: Add patterns to generate 'combine' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 17:16:38 +00:00
Jyotsna Verma
91eadc6d69 Hexagon: ArePredicatesComplement should not restrict itself to TFRs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 16:36:34 +00:00
Jyotsna Verma
9c9bf9a240 Hexagon: Remove dead-code after unconditional return from addPreSched2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 15:33:27 +00:00
Duncan Sands
b99052ce4a Suppress GCC compiler warnings in release builds about variables that are only 
read in asserts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 07:50:47 +00:00
Rafael Espindola
4a971705bc Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 01:16:13 +00:00
Rafael Espindola
d84ccfaf50 Change getFrameMoves to return a const reference. 
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-11 02:38:11 +00:00
Jyotsna Verma
fd4ccda4a5 Fix unused variable error. 
Earlier, this variable was used in an assert and was causing failure on
darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 21:44:02 +00:00
Jyotsna Verma
cdfb55d15b Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 20:58:11 +00:00
Jyotsna Verma
1a35b8e2eb Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 20:27:34 +00:00
Rafael Espindola
6e53180db1 Remove unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 18:16:59 +00:00
Rafael Espindola
3a0d00eef9 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 16:53:12 +00:00
Jyotsna Verma
80d81aa8ba Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181535 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-09 19:16:07 +00:00
Jyotsna Verma
f4f60b10e4 Hexagon: Use relation map for getMatchingCondBranchOpcode() and 
getInvertedPredicatedOpcode() functions instead of switch cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-09 18:25:44 +00:00
Jyotsna Verma
f931f691ee Hexagon: Fix Small Data support to handle -G 0 correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 19:53:00 +00:00
Jyotsna Verma
ddcf3ee768 Reverting r181331. 
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 17:12:35 +00:00
Jyotsna Verma
81fda3b4d5 Hexagon: Fix Small Data support to handle -G 0 correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 16:42:15 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 15:06:29 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 21:58:00 +00:00
Krzysztof Parzyszek
b072090f39 Cleanup of the HexagonTargetMachine setup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 21:25:45 +00:00
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
ed6fe299cf Make references to HexagonTargetMachine "const". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:38:37 +00:00
Krzysztof Parzyszek
cc420a0911 Use consistent function names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-04 01:30:49 +00:00
Reid Kleckner
aa35a56975 Fix missing include in Hexagon code for Release+Asserts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 00:54:56 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 22:10:59 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:21:57 +00:00