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6a86bd71df
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10131 Commits

Author SHA1 Message Date
Evan Cheng
6a86bd71df Implement multiple with overflow by 2 with an add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63090 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 03:30:42 +00:00
Dan Gohman
e8ecf4876a Eliminate unnecessary operands-list traversals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63088 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 02:37:43 +00:00
Dan Gohman
499cb3fcfb Enable the red zone on x86-64 by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63078 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 00:58:47 +00:00
Dan Gohman
336b636dd7 Fix the Red Zone calculation for functions with frame pointers. 
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 00:40:06 +00:00
Scott Michel
9de57a9ed2 CellSPU: 
- Update DWARF debugging support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63059 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 22:33:37 +00:00
Scott Michel
210de72cd7 Make the Dwarf macro information section optional; CellSPU's assembler 
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63058 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 22:32:51 +00:00
Dan Gohman
92f4f16a19 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63056 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 22:22:31 +00:00
Evan Cheng
5b2e5893c6 Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 18:43:34 +00:00
Dan Gohman
e7852d0144 Take the next steps in making SDUse more consistent with LLVM Use, and 
tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62995 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 04:35:06 +00:00
Scott Michel
19c10e658a Untabify code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62991 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 03:37:41 +00:00
Scott Michel
c9c8b2a804 CellSPU: 
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 03:31:40 +00:00
Nate Begeman
5bf4b7556f Fix a typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62989 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 03:15:54 +00:00
Nate Begeman
c2fd67f697 De-identifying per sabre review 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 03:15:31 +00:00
Nate Begeman
51a0437b16 Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 01:24:32 +00:00
Nate Begeman
740ab03f12 Support pattern matching various x86 sse shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 00:52:55 +00:00
Chris Lattner
4469c53cfc silence a warning when assertions are disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62976 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 23:08:00 +00:00
Torok Edwin
afb564c697 should have removed the + when manually applying a patch! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62973 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 20:29:34 +00:00
Torok Edwin
c8ad2d2abf revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 20:21:24 +00:00
Torok Edwin
7f1d5252c7 If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62967 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 17:58:56 +00:00
Evan Cheng
1902a129a5 Private linkage support for PPC / Darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62955 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 06:32:01 +00:00
Nate Begeman
9b99485074 Fix an indent and a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-24 22:12:48 +00:00
Torok Edwin
e46a686dc2 add note about possible GEP improvement with fields of size 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62925 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-24 19:30:25 +00:00
Chris Lattner
91387de8ce hopefully address PR3379 by making the P modifier work in x86 inline asm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62887 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-23 22:33:40 +00:00
Bob Wilson
4c24546238 Add SelectionDAG::getNOT method to construct bitwise NOT operations, 
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62768 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 17:39:32 +00:00
Evan Cheng
536ab130ec Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 09:10:11 +00:00
Chris Lattner
256baa4b1f add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62760 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 07:16:03 +00:00
Dan Gohman
dbf5f2557e Recognize inline asm for bswap on x86-64 GLIBC. This allows it 
to be supported in the JIT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62730 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 23:40:54 +00:00
Evan Cheng
a095c972cc Also favors NOT64r. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62710 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 19:45:31 +00:00
Chris Lattner
0f2d995fd6 fix warning in release-asserts mode and spelling of assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62699 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 18:38:18 +00:00
Dan Gohman
1ef4d8f7ee Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 14:50:16 +00:00
Sanjiv Gupta
2530566acd Fixed build warnings. Restoring changes done in 62600, they were lost in 62655. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62681 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 09:02:46 +00:00
Duncan Sands
9fbc7e2e7a Cleanup whitespace and comments, and tweak some 
prototypes, in operand type legalization.  No
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62680 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 09:00:29 +00:00
Sanjiv Gupta
08b9b05218 Implement LowerOperationWrapper for legalizer. 
Also a few signed comparison fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62665 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 05:44:05 +00:00
Scott Michel
d1e8d9c0a5 CellSPU: 
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 04:58:48 +00:00
Evan Cheng
aaf414c92c Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62661 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 02:09:05 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 19:12:24 +00:00
Dan Gohman
8289b05c4c Add a README entry noticed while investigating PR3216. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 01:07:33 +00:00
Evan Cheng
2722e7b139 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 19:06:11 +00:00
Evan Cheng
c1a168a0fc Fix 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 18:57:29 +00:00
Evan Cheng
5fc742d5b2 Handle ISD::DECLARE with PIC relocation model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62516 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 18:31:51 +00:00
Evan Cheng
50c3dfefd9 Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. 
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62505 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 08:19:57 +00:00
Evan Cheng
a06ec9efe1 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 08:08:22 +00:00
Bill Wendling
030939c87b Extend thi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62415 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:40:19 +00:00
Evan Cheng
8e27826649 Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:09:27 +00:00
Bill Wendling
f6a4e2edb0 Temporarily revert my last change. It is causing a bootstrap failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 04:23:51 +00:00
Bill Wendling
8b8a636843 Implement a special algorithm for converting uint_to_fp for i32 values on 
X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62404 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 03:56:04 +00:00
Oscar Fuentes
70fd453a02 CMake: Add lib/Target/IA64/IA64Subtarget.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62394 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 01:50:32 +00:00
Evan Cheng
ee5c2b8ba2 Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 22:57:32 +00:00
Dan Gohman
01bbc3e334 Give IA64 a TargetSubtarget subclass, so that it can 
implement getSubtargetImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 22:49:36 +00:00
Bill Wendling
64e87326d9 Add support for non-zero __builtin_return_address values on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 19:25:27 +00:00