Jim Grosbach
3efad8fad4
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 19:11:16 +00:00
Jim Grosbach
d40963c406
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:28:03 +00:00
Jim Grosbach
40edf73a62
Refactor a bit for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:10:47 +00:00
Jim Grosbach
eb61272150
Make sure to propagate the predicate operands for LEApcrel to ADR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:45:47 +00:00
Bill Wendling
f4caf69720
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
Owen Anderson
a838a25d59
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:36:49 +00:00
Jim Grosbach
766a63d20e
Add a textual message to the assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:23:51 +00:00
Jim Grosbach
9702e6075c
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
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referencing the stack pointer as they say they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:22:19 +00:00
Jim Grosbach
dff84b0325
Add support for binary encoding of ARM 'adr' instructions referencing constant
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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 00:28:45 +00:00
Jim Grosbach
5d14f9be7b
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
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instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:47:31 +00:00
Jim Grosbach
baf120fbe8
Move the ARMAsmPrinter class defintiion into a header file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 03:45:07 +00:00
Jim Grosbach
2e812e1635
Pseudo-ize ARM MOVPCRX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:56:36 +00:00
Jim Grosbach
a0d2c8a40f
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
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rdar://8685712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:30:19 +00:00
Bill Wendling
6e46d84eea
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:48:15 +00:00
Jim Grosbach
5ca66696e7
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
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instructions. This simplifies instruction printing and disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:37:40 +00:00
Jim Grosbach
d092a87ba3
Rename t2 TBB and TBH instructions to reference that they encode the jump table
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data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 21:28:32 +00:00
Jim Grosbach
f1aa47dc1a
ARM Pseudo-ize tBR_JTr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:32:47 +00:00
Jim Grosbach
2dc7768d73
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:37:44 +00:00
Jim Grosbach
f8dabac604
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
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in the MC lowering process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 21:05:55 +00:00
Jim Grosbach
11bbeecdf1
Add FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 18:36:48 +00:00
Chris Lattner
2ac190238e
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:05 +00:00
Chris Lattner
30e2cc254b
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:00:02 +00:00
Chris Lattner
1612a619f1
even more simplifications. ARM MCInstLowering is now just
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a single function instead of a class. It doesn't need the
complexity that X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:58:38 +00:00
Chris Lattner
112f2390e1
simplify and tidy up
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:31:06 +00:00
Jim Grosbach
7c7ddb21c3
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
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double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
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VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 03:26:07 +00:00
Jim Grosbach
3a2429a86c
Change the ARMConstantPoolValue modifier string to an enumeration. This will
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help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f
Handle ARM constant pool values that need an explicit reference to the '.'
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pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:40:22 +00:00
Jim Grosbach
5df08d8f55
Further MCize ARM constant pool values. This allows basic PIC references for
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object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:45:04 +00:00
Dale Johannesen
7179d1e5c0
Revert 118422 in search of bot verdancy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 17:58:07 +00:00
Jim Grosbach
ce79299f78
MC'ize the '.code 16' and '.thumb_func' ARM directives.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:08:08 +00:00
Jim Grosbach
8da0a5785c
MC'ize simple ARMConstantValue entry emission (with a FIXME).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 20:34:24 +00:00
Jim Grosbach
6d87bca865
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 17:37:13 +00:00
Jim Grosbach
8e0a3eb957
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
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the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:35:25 +00:00
Jim Grosbach
a3c1629ff5
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
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handle it in the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:37:06 +00:00
Jim Grosbach
7e3383c007
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:12:14 +00:00
Jim Grosbach
c1d30212e9
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:19:44 +00:00
Jim Grosbach
3e55612472
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:37:02 +00:00
Rafael Espindola
3336384239
Produce the headers directly in the Finish method. This allows us to use
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the existing streamer methods that are endian safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:26:55 +00:00
Rafael Espindola
4921e2356e
Add a virtual destructor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:38:32 +00:00
Rafael Espindola
cecbc3d282
Add support for emitting ARM file attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:50:35 +00:00
Jason W Kim
17b443df43
Second set of ARM/MC/ELF changes.
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Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:01:44 +00:00
Jim Grosbach
fa7fb64fad
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7
First in a sequence of ARM/MC/*ELF* specific work.
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Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:36:46 +00:00
Jim Grosbach
1d6111c5ac
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
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"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:22:32 +00:00
Jim Grosbach
4dea941c8d
target operand flag values aren't a bitmask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 16:51:55 +00:00
Jim Grosbach
78890f41f4
Nuke the rest of the :comment references
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:21:38 +00:00
Jim Grosbach
7ac1609a3b
Rename the AsmPrinter directory to InstPrinter for those targets that have
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:39:28 +00:00