Commit Graph

2572 Commits

Author SHA1 Message Date
Vladimir Medic
764f6f5125 This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 09:28:35 +00:00
Vladimir Medic
16f385f90f Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-17 14:05:19 +00:00
Joey Gouly
c88ac4a344 Add the tests that I forgot to 'svn add' with my previous commit (r186504).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-17 14:03:49 +00:00
Tilmann Scheller
898788c6bc ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]

See A8.8.129 in the ARM ARM (DDI 0406C.b).

Fixes <rdar://problem/14403733>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 21:52:34 +00:00
Richard Sandiford
c25d21e05b [SystemZ] Add MC support for R[NOX]SBG
CodeGen support will come later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 11:28:08 +00:00
Reid Kleckner
6057eb7ab6 [mc-coff] Resolve aliases when emitting COFF relocations
This is consistent with the ELF object writer.

Add some COFF tests that relocate against an alias.

Reviewers: espindola

Differential Revision: http://llvm-reviews.chandlerc.com/D1079

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 19:41:21 +00:00
Stephen Lin
0dfc166487 Add newlines at end of test files, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-13 22:00:58 +00:00
Vladimir Medic
dd51a0c1e0 Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 09:25:35 +00:00
Richard Sandiford
3ee0673e4f [SystemZ] Allow 8-bit operands to RISBG
RISBG has three 8-bit operands (I3, I4 and I5).  I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time.  However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-11 08:37:13 +00:00
Tim Northover
f5b1c5043d Put ELF COMDAT relocations into the relevant COMDAT group.
Patch from Игорь Пашев  (I do hope we support utf-8 commit messages; I
also hope he'll forgive me for transliterating it as Igor Pashev in
case things go horribly wrong).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 20:58:17 +00:00
Vladimir Medic
faf98904b7 Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186001 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 12:27:25 +00:00
Vladimir Medic
2ec5933eae Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 10:18:10 +00:00
Ulrich Weigand
7a34599db0 [PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:

>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout.  (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)

This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.

This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined.  This means shared libraries
using TLS built with the integrated assembler are currently
broken.

While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit.  Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.

To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now.  One the underlying
problem is fixed, this hack can be reverted again.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185945 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 16:41:09 +00:00
Joey Gouly
12f45c3782 Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 11:26:18 +00:00
Joey Gouly
8dc741d29f Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 11:03:21 +00:00
Ulrich Weigand
b2713e018e [PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.

However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 10:00:34 +00:00
Joey Gouly
9fb5a6588b Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 09:59:04 +00:00
Ulrich Weigand
ff16df71f5 [PowerPC] Support .llong and fix .word
This adds support for the .llong PowerPC-specifc assembler directive.
In doing so, I notices that .word is currently incorrect: it is
supposed to define a 2-byte data element, not a 4-byte one.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185911 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 07:59:25 +00:00
Eric Christopher
01e4509972 CEHCK->CHECK typo fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185875 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 21:47:33 +00:00
Eric Christopher
193a2da6d1 Fix up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 21:47:31 +00:00
Ulrich Weigand
19d2b78978 [PowerPC] Support time base instructions
This adds support for the old-style time base instructions;
while new programs are supposed to use mfspr, the mftb instructions
are still supported and in use by existing assembler files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 15:20:38 +00:00
Ulrich Weigand
9e5bbeab1f [PowerPC] Support basic compare mnemonics
This adds support for the basic mnemoics (with the L operand) for the
fixed-point compare instructions.  These are defined as aliases for the
already existing CMPW/CMPD patterns, depending on the value of L.

This requires use of InstAlias patterns with immediate literal operands.
To make this work, we need two further changes:

 - define a RegisterPrefix, because otherwise literals 0 and 1 would
   be parsed as literal register names

 - provide a PPCAsmParser::validateTargetOperandClass routine to
   recognize immediate literals (like ARM does)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 14:49:37 +00:00
Kai Nacke
5310cdbcc9 Revert: Fix wrong code offset for unwind code SET_FPREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 04:48:34 +00:00
Kai Nacke
9611873724 Revert: Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH data structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185791 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 04:46:55 +00:00
Kai Nacke
9c411e649e Revert: Fix alignment of unwind data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 04:45:05 +00:00
Joey Gouly
2a9683289b Add MC support for the v8fp instructions: vmaxnm and vminnm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 20:50:18 +00:00
Kai Nacke
59c5c6c2b2 Fix alignment of unwind data.
For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).

Reviewed by Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 17:16:50 +00:00
Kai Nacke
eececbc7d3 Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
data structures.

The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.

Reviewed by Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 17:16:12 +00:00
Kai Nacke
ea434e4bca Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s

Reviewed by Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 17:15:36 +00:00
Nico Rieck
8064628379 MC: Implement COFF .linkonce directive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 12:13:10 +00:00
Ulrich Weigand
457571ed69 [PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.

However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.

The same applies for the @got@dtprel variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 13:49:46 +00:00
Ulrich Weigand
3d4427347e [PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis.  Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.

Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 12:33:03 +00:00
Ulrich Weigand
23a72c8f7e [PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
   add 3, 4, symbol@tls

The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant.  This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS.  This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.

As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 12:22:36 +00:00
Nico Rieck
a6d343a688 MC: Add .section directive to COFF
Supports GAS flags "abdnrswxy". No support for alignment or subsections.

Fixes PR16366.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 21:32:07 +00:00
Ulrich Weigand
972befb3f2 [PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.

This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 18:28:46 +00:00
Rafael Espindola
449f64c69c Add 'not' in front of a command that is expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 17:21:01 +00:00
Joey Gouly
4ea250524f Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:57:20 +00:00
Ulrich Weigand
3c99602ca8 [PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:40:12 +00:00
Ulrich Weigand
5606fcae50 [PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:24:00 +00:00
Joey Gouly
929d9ef111 Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 10:04:08 +00:00
Tilmann Scheller
79c163d6dd ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.

The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.

This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.

Fixes <rdar://problem/14224440>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 20:38:01 +00:00
Ulrich Weigand
51f558c9ae [PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 18:29:47 +00:00
Ulrich Weigand
33efedc048 [PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 17:59:07 +00:00
Rafael Espindola
73477b9f32 Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 16:41:29 +00:00
Ulrich Weigand
44175d9715 [PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 12:32:41 +00:00
Mihai Popa
b81b477cd4 This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 09:21:44 +00:00
Ulrich Weigand
25b9bbae69 [PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser.  This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop.  That pattern is used for the
asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 21:31:59 +00:00
Richard Sandiford
9188443a2d [SystemZ] Add the MVC instruction
This is the first use of D(L,B) addressing, which required a fair bit
of surgery.  For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 14:56:45 +00:00
Logan Chien
0a39e26433 Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes.  The handler data consists of several words, and
should be terminated by zero.

In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 12:43:27 +00:00
Hal Finkel
75dd57a8f0 Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:

1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.

2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).

3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.

4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.

With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 03:39:34 +00:00