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Commit Graph

25756 Commits

Author SHA1 Message Date
Hal Finkel
05a4d2642b PPC: Map frin to round() not nearbyint() and rint()
Making use of the recently-added ISD::FROUND, which allows for custom lowering
of round(), the PPC backend will now map frin to round(). Previously, we had
been using frin to lower nearbyint() (and rint() via some custom lowering to
handle the extra fenv flags requirements), but only in fast-math mode because
frin does not tie-to-even. Several users had complained about this behavior,
and this new mapping of frin to round is certainly more appropriate (and does
not require fast-math mode).

In effect, this reverts r178362 (and part of r178337, replacing the nearbyint
mapping with the round mapping).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 04:31:34 +00:00
Hal Finkel
41418d17cc Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.

For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).

This will be used by the PowerPC backend in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 22:49:12 +00:00
Elena Demikhovsky
207600d2cf AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 12:34:55 +00:00
Richard Sandiford
29e873ddb6 [SystemZ] Optimize floating-point comparisons with zero
This follows the same lines as the integer code.  In the end it seemed
easier to have a second 4-bit mask in TSFlags to specify the compare-like
CC values.  That eats one more TSFlags bit than adding a CCHasUnordered
would have done, but it feels more concise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:10:06 +00:00
Richard Sandiford
e0bbf7288c [SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:03:34 +00:00
Craig Topper
b19982c42b Simplify code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187870 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 08:16:07 +00:00
Evgeniy Stepanov
8f3562bc6b Initialize SIInsertWaits::ExpInstrTypesSeen in the pass constructor.
This value may be used uninitialized in SIInsertWaits::insertWait.
Found with MemorySanitizer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 07:47:41 +00:00
Reed Kotler
51c9043f3b Create a pattern for the "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 04:00:26 +00:00
David Blaikie
040ef013ac Remove unused functions introduced in r172685 to unbreak the Clang -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 00:25:12 +00:00
Tom Stellard
c89c964499 R600: Add new file from r187831 to CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:12:34 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Tom Stellard
3492eefa4b R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:

SGPR = COPY VGPR

Will now be emitted like this:

VSrC = COPY VGPR

This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur.  Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:28 +00:00
Tom Stellard
3406d882c0 R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:18 +00:00
Justin Holewinski
06d63b31be [NVPTX] We dont have any target specific flags yet for generating symbol references, so get rid of the default-only switch statement. Fixes an MSVC warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:06:42 +00:00
Akira Hatanaka
6b034bb3ae [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:01:10 +00:00
Akira Hatanaka
014096e4d5 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:35:29 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:20:40 +00:00
Hal Finkel
0e910d2cb5 Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 17:03:03 +00:00
Mihai Popa
4f7092176c This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 16:07:46 +00:00
Mihai Popa
4a378b95aa Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 15:52:36 +00:00
Justin Holewinski
df66ff09bc [NVPTX] Add missing patterns for i1 [s,u]int_to_fp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:34 +00:00
Justin Holewinski
a3635eefc7 [NVPTX] Fix bug in stack code generation causes by MC conversion
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:31 +00:00
Justin Holewinski
82767327c5 [NVPTX] Start conversion to MC infrastructure
This change converts the NVPTX target to use the MC infrastructure
instead of directly emitting MachineInstr instances. This brings
the target more up-to-date with LLVM TOT, and should fix PR15175
and PR15958 (libNVPTXInstPrinter is empty) as a side-effect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 14:13:27 +00:00
Tim Northover
8775a51d94 ARM: implement allowTruncateForTailCall
Now that it's in place, it seems silly not to let ARM make use of the extra
tail call opportunities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187795 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 13:58:03 +00:00
Tim Northover
d113448c1d Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:

define i64 @test1(i64 %val) {
  %in = trunc i64 %val to i32
  tail call i32 @ret32(i32 returned %in)
  ret i64 %val
}

define i64 @test2(i64 %val) {
  tail call i32 @ret32(i32 returned undef)
  ret i32 42
}

should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.

For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
   than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
   call.

Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).

This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.

Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 09:12:35 +00:00
Craig Topper
5923547e2a Simplify vector lane handling math a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 07:23:12 +00:00
Craig Topper
57bc5a0b5b Simplify math a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:54:25 +00:00
NAKAMURA Takumi
8e1d64666f Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:38:37 +00:00
Craig Topper
aa0f420567 Replace EVT with MVT in isHorizontalBinOp as it is only called with legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:05:05 +00:00
Craig Topper
20b46b0733 Simplify code slightly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 04:12:40 +00:00
Tom Stellard
01d7203ef8 Factor FlattenCFG out from SimplifyCFG
Patch by: Mei Ye

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 02:43:45 +00:00
Tom Stellard
2b272a1c8c R600: Implement TargetLowering::getVectorIdxTy()
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 22:22:07 +00:00
Aaron Ballman
2a37c7e9e6 Silencing an MSVC11 type conversion warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 13:47:03 +00:00
Richard Sandiford
9379557478 [SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequences
This patch just uses a peephole test for "add; compare; branch" sequences
within a single block.  The IR optimizers already convert loops to
decrement-and-branch-on-nonzero form in some cases, so even this
simplistic test triggers many times during a clang bootstrap and
projects/test-suite run.  It looks like there are still cases where we
need to more strongly prefer branches on nonzero though.  E.g. I saw a
case where a loop that started out with a check for 0 ended up with a
check for -1.  I'll try to look at that sometime.

I ended up adding the Reference class because MachineInstr::readsRegister()
doesn't check for subregisters (by design, as far as I could tell).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:23:46 +00:00
Richard Sandiford
ccdf5cc7bc [SystemZ] Add definitions for BRCT and BRCTG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:07:38 +00:00
Richard Sandiford
9b05c709c6 [SystemZ] Use LOAD AND TEST to eliminate comparisons against zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187720 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:03:20 +00:00
Richard Sandiford
0e4044c233 [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:00:53 +00:00
Richard Sandiford
66fbb47818 [SystemZ] Split out comparison elimination into a separate pass
Perhaps predictably, doing comparison elimination on the fly during
SystemZLongBranch turned out to be a bad idea.  The next patches make
use of LOAD AND TEST and BRANCH ON COUNT, both of which require
changes to earlier instructions.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 10:58:53 +00:00
Elena Demikhovsky
13e6e9171f AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 08:52:21 +00:00
Reed Kotler
25278aa26f Add the saving of S2. This is needed for some of the floating point
helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 23:56:53 +00:00
Benjamin Kramer
75311b7b4d X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }

before:
_test:
	ucomisd	%xmm0, %xmm1
	ja	LBB0_2
	movaps	%xmm3, %xmm2
LBB0_2:
	movaps	%xmm2, %xmm0

after:
_test:
	cmpltsd	%xmm1, %xmm0
	andpd	%xmm0, %xmm2
	andnpd	%xmm3, %xmm0
	orpd	%xmm2, %xmm0

Small speedup on Benchmarks/SmallPT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 12:05:16 +00:00
Elena Demikhovsky
f3e3417e65 AVX-512 set: added VEXTRACTPS instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 10:46:07 +00:00
Tim Northover
a54b66277e X86: correct tail return address calculation
Due to the weird and wondeful usual arithmetic conversions, some
calculations involving negative values were getting performed in
uint32_t and then promoted to int64_t, which is really not a good
idea.

Patch by Katsuhiro Ueno.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 09:35:57 +00:00
Reed Kotler
8a7f9de9d4 Clean up code for Mips16 large frame handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 01:13:25 +00:00
Benjamin Kramer
af00feb1a6 PPCAsmParser: Stop leaking names.
Store them in a place that gets cleaned up properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-03 22:43:29 +00:00
Benjamin Kramer
527692a594 ARMAsmParser: Plug a leak.
Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-03 22:16:24 +00:00
Benjamin Kramer
bc2160f7c9 Stop leaking register infos in the disassemblers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-03 22:16:16 +00:00
Hal Finkel
5cad12d12a Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.

At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-03 12:25:10 +00:00
Joey Gouly
e7bc73b8d1 Add a missing 'return' statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187671 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 20:50:01 +00:00
Akira Hatanaka
5e795097b0 [mips] Expand vector truncating stores and extending loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 19:23:33 +00:00