Dale Johannesen
fb88f1f9a7
Remove unneeded stuff from GRAD register class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-14 18:10:48 +00:00
Dale Johannesen
330169fa3e
Extend InlineAsm::C_Register to allow multiple specific registers
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(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 21:52:36 +00:00
Evan Cheng
9ed08f4a41
Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31 16:52:57 +00:00
Evan Cheng
ae270f66aa
ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53208 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07 22:21:06 +00:00
Dale Johannesen
a68f9013f2
Add v2f32 (MMX) type to X86. Support is primitive:
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load,store,call,return,bitcast. This is enough to
make call and return work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-24 22:01:44 +00:00
Christopher Lamb
1fab4a6bbb
Recommitting parts of r48130. These do not appear to cause the observed failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 10:09:17 +00:00
Evan Cheng
204496d58e
In 32-bit mode, mark 64-bit GPR's as unallocatable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 07:16:00 +00:00
Chris Lattner
8e6da15e54
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
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copyfromreg/copytoreg instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 21:08:41 +00:00
Evan Cheng
4499e495ea
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 19:31:26 +00:00
Christopher Lamb
3feb0170a8
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 06:12:08 +00:00
Chris Lattner
8dc023f684
claim ST(x) registers are 80 bits, which is true. This doesn't affect
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codegen yet because these can't be spilled (they don't exist until after RA).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:49:01 +00:00
Dan Gohman
6f0d024a53
Rename MRegisterInfo to TargetRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Anton Korobeynikov
8eea339298
Provide correct DWARF register numbering for debug information emission on x86-32/Darwin.
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This should fix bunch of issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46337 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-25 00:34:13 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Anton Korobeynikov
f191c80cd7
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11 19:50:10 +00:00
Dale Johannesen
7a42f24f0c
Revert previous rewrite per chris's comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43950 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-09 18:07:11 +00:00
Dale Johannesen
3556bc1a9d
Rewrite Dwarf number handling per review comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43918 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-09 00:47:10 +00:00
Dale Johannesen
4542edcaa7
Complete conditionalization of Dwarf reg numbers.
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Would somebody not on Darwin please make sure this
doesn't break anything. Exception handling failures
would be the most likely symptom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43844 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-07 21:48:35 +00:00
Arnold Schwaighofer
48abc5cf6b
Corrected many typing errors. And removed 'nest' parameter handling
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for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12 21:30:57 +00:00
Evan Cheng
dcfa73fe3c
Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42124 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19 01:36:39 +00:00
Evan Cheng
3054dde813
Added status flags register: EFLAGS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41862 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 19:53:28 +00:00
Evan Cheng
a3231ba237
Temporarily backing out this change until we know why some dejagnu tests are failing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-09 22:25:35 +00:00
Evan Cheng
a333b41af9
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-09 18:05:17 +00:00
Dale Johannesen
59a587337e
Long double patch 4 of N: initial x87 implementation.
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Lots of problems yet but some simple things work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-05 18:49:15 +00:00
Christopher Lamb
f9b90ea955
Add register info needed to use subreg sets on X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40572 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-28 19:03:30 +00:00
Dale Johannesen
849f214a4e
Fix for PR 1505 (and 1489). Rewrite X87 register
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model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-03 00:53:03 +00:00
Anton Korobeynikov
038082d966
Emit correct DWARF reg # for RA (return address) register
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36646 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 08:46:03 +00:00
Evan Cheng
6120433e9e
Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36279 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 21:15:21 +00:00
Bill Wendling
eebc8a1bc5
Add support for the v1i64 type. This makes better code for this:
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#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26 07:53:08 +00:00
Evan Cheng
dc77540d95
hasFP() is now a virtual method of MRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-23 00:57:47 +00:00
Evan Cheng
25ab690a43
Committing X86-64 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 06:48:29 +00:00
Chris Lattner
5ea64fd9eb
Constify some methods. Patch provided by Anton Vayvod, thanks!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 22:00:08 +00:00
Evan Cheng
e46e1a5da7
Make XMM, FP register dwarf register numbers consistent with gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29543 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-07 21:02:39 +00:00
Jim Laskey
6b59a36564
Get darwin intel debugging up and running.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29504 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-03 17:27:09 +00:00
Evan Cheng
069287d460
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 07:21:53 +00:00
Evan Cheng
403be7eafc
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
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movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-08 08:01:26 +00:00
Evan Cheng
74811450b2
Typo's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28158 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-07 10:10:20 +00:00
Jim Laskey
47622e3721
Add dwarf register numbering to register data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:15:58 +00:00
Evan Cheng
5c791c8ba4
Junk unused vector register classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26910 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 00:30:59 +00:00
Evan Cheng
933be3318b
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
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Added generic vector types: VR64 and VR128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 01:38:21 +00:00
Evan Cheng
aea20f50e5
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
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packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-20 22:34:53 +00:00
Evan Cheng
71fb9ad5d9
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
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SDNPOutFlag, and SDNPOptInFlag instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25629 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 00:29:36 +00:00
Evan Cheng
5bc4da4893
Bye bye HACKTROCITY.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24935 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22 02:26:21 +00:00
Evan Cheng
b077b842b6
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 02:39:21 +00:00
Evan Cheng
bbc8ddbea3
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24886 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 22:59:51 +00:00
Evan Cheng
aed7c721df
Added support for cmp, test, and conditional move instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:24:02 +00:00
Nate Begeman
6510b22cec
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
Nate Begeman
14e2cf62f4
Properly split f32 and f64 into separate register classes for scalar sse fp
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fixing a bunch of nasty hackery
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 22:06:00 +00:00
Chris Lattner
ecbce617ca
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 19:13:20 +00:00
Chris Lattner
03ba7b9f25
Put register classes into namespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22925 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:51:57 +00:00