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Author SHA1 Message Date
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:32 +00:00
Devang Patel
fd56f3c91a This is x86 only test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:17:38 +00:00
Daniel Dunbar
ee0f32d723 configure: Add detection of the linker version string. 
- Review appreciated, as long as you understand that I understand that this is
   a horrible hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:53:59 +00:00
Johnny Chen
7def14f40f Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:35:12 +00:00
Devang Patel
ebd53742c6 Even if a variable has constant value all the time, it is still a variable in gdb's eyes. 
Tested by scope.exp in gdb testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:17:54 +00:00
Bob Wilson
eaf1c98a7c Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:10:46 +00:00
Jakob Stoklund Olesen
d29583bd32 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:08:22 +00:00
Owen Anderson
cf6abd2486 Fix a subtle use-after-free issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110863 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 22:36:04 +00:00
Nick Lewycky
7f9ef4bb51 Clean up ConstantRange a bit: 
- remove ashr which never worked.
 - fix lshr and shl and add tests.
 - remove dead function "intersect1Wrapped".
 - add a new sub method to subtract ranges, with test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 22:04:36 +00:00
Bruno Cardoso Lopes
4fd393cc26 Add testcases for all AVX 256-bit intrinsics added in the last couple days 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 21:12:09 +00:00
Dan Gohman
bd4d66d56a Make LoopPass::getContainedPass return a LoopPass* instead of a Pass* 
and remove casts from all its callers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 20:34:43 +00:00
Dan Gohman
fa5c2a67c3 Remove BasicBlockPass::runOnFunction, which was unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 20:28:16 +00:00
Bruno Cardoso Lopes
ec1355b17b Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 19:21:05 +00:00
Dan Gohman
1f9a1608a6 Delete FunctionPass::run, which is unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 19:11:05 +00:00
Dan Gohman
73e8800229 Delete FunctionPass::runOnModule, which is unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 19:05:53 +00:00
Dan Gohman
b68f274b6d Don't use unsigned char for alignments in TargetData. There aren't 
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 18:15:01 +00:00
Dan Gohman
d881627d33 Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 18:14:00 +00:00
Bruno Cardoso Lopes
1d72aeebf9 Reapply r109881 using a more strict command line for llc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:39:23 +00:00
Jim Grosbach
b5aa11f2d6 fix silly typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:32:46 +00:00
Jim Grosbach
7166e622d7 Add a target triple, as the runtime library invocation varies a bit by 
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:31:12 +00:00
Evan Cheng
e1f0859789 Fix test and re-enable it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:25:51 +00:00
Jakob Stoklund Olesen
dfa28b157d Fix a FIXME. The SlotIndex::Slot enum should be private. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 16:50:17 +00:00
Dan Gohman
3cc5d13f58 Temporarily disable some failing tests, until they can be 
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 16:36:07 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 15:44:15 +00:00
Dan Gohman
f63fed141e Temporarily disable some failing tests, until they can be 
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 15:09:00 +00:00
Bill Wendling
de2b151dbf Consider this code snippet: 
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:17:46 +00:00
Evan Cheng
8d62e713ea ArchV7M implies HW division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:00:16 +00:00
Evan Cheng
cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:57:53 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:51:54 +00:00
Daniel Dunbar
345a9a6269 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:20 +00:00
Daniel Dunbar
5747b13af8 MC/ARM: Split mnemonic on '.' characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:16 +00:00
Daniel Dunbar
fa315de8f4 MC/ARM: Fill in ARMOperand::dump a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:12 +00:00
Daniel Dunbar
3c14ca47fc llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:09 +00:00
Daniel Dunbar
b3cb696794 MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:04 +00:00
Daniel Dunbar
4d39b6728d tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:59 +00:00
Daniel Dunbar
8462b30548 MC/ARM: Add an ARMOperand class for condition codes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:53 +00:00
Evan Cheng
ee34987fd5 Really control isel of barrier instructions with cpu feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:31 +00:00
Evan Cheng
c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:30:38 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:22:01 +00:00
Daniel Dunbar
3483acabf0 MC/ARM: Switch to using the generated match functions instead of stub implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 05:24:50 +00:00
Daniel Dunbar
a7ac688d55 MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 05:09:20 +00:00
Daniel Dunbar
3bcd9f7902 ARM: Mark some disassembler only instructions as not available for matching -- 
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:13 +00:00
Daniel Dunbar
9db683b06c ARM: Quote $p in an asm string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:10 +00:00
Daniel Dunbar
a9ba5fe2bd tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:08 +00:00
Owen Anderson
2d0f2470ff Improve indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:24:25 +00:00
Bruno Cardoso Lopes
1a76359347 Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes
9fb2ffd568 Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:44:11 +00:00
Bruno Cardoso Lopes
b89c631b77 Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:18:26 +00:00
Bill Wendling
d771041828 Update test to match output of optimize compares for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:05:02 +00:00