Commit Graph

2660 Commits

Author SHA1 Message Date
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 00:22:00 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 23:09:09 +00:00
Jim Grosbach
0e387b2877 ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:26:03 +00:00
Owen Anderson
684dfcf724 Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 16:56:47 +00:00
Benjamin Kramer
af482cf301 Pick low-hanging MatchEntry shrinkage fruit.
Shaves 200k off Release-Asserts clang binaries on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 16:18:09 +00:00
Craig Topper
ee62e4f6d1 Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
Craig Topper
17730847d5 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
Craig Topper
566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
Craig Topper
54a11176f6 Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
Jakob Stoklund Olesen
ccbe603869 Ban rematerializable instructions with side effects.
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 01:00:49 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Eli Friedman
830378f662 Remove extra semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 19:53:40 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
Jakob Stoklund Olesen
819a2abc72 Emit full ED initializers even for pseudo-instructions.
This should unbreak the picky buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 20:15:49 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd Insert dummy ED table entries for pseudo-instructions.
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:30:16 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
Peter Collingbourne
6d1409dcc5 Remove the Clang tblgen backends from LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 13:21:42 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 01:51:51 +00:00
Jakob Stoklund Olesen
d9c1fa5205 Remove the TRI::getSubRegisterRegClass() hook.
This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 00:08:27 +00:00
Jakob Stoklund Olesen
845d2c0c77 Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 00:35:49 +00:00
Jakob Stoklund Olesen
dae7909be3 Properly use const_iterator.
This should unbreak the Windows build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:18:39 +00:00
Jakob Stoklund Olesen
babf0569e2 Teach TableGen to infer missing register classes.
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:49 +00:00
Jakob Stoklund Olesen
cc0c975b7d TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:44 +00:00
Jakob Stoklund Olesen
6fea31e730 TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:08 +00:00
Jakob Stoklund Olesen
877b6d43d4 TableGen: Don't add synthetic Records to the RecordKeeper.
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:27:53 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
Craig Topper
42fbe9aa06 Fix typo in r140954.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 04:54:26 +00:00
Craig Topper
846a2dcada Fix disassembling of INVEPT and INVVPID to take operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
Peter Collingbourne
7c78888887 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 16:41:13 +00:00
Bob Wilson
1cea66c3ba Subtarget getFeatureBits() returns a uint64_t, not unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 02:47:54 +00:00
Jakob Stoklund Olesen
52e7dfadc6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
All the sub-class bit vectors are computed when first creating the
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen
c8e2bb68bb Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
b7359e384f Extract a slightly more general BitVector printer.
This one can also print 32-bit groups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
f9a4bb78da Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:18:45 +00:00
David Greene
1045a594e6 Implement VarListElementInit:: resolveListElementReference
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen
203e0b17dd Precompute a bit vector of register sub-classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
7dcaa5b0fb Order register classes topologically.
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
29f018cee6 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:28:37 +00:00
Daniel Dunbar
caf1912893 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
"show-in-system-header" bits, which I will be adding in Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 00:29:04 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen
c291e2f578 Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25 19:21:35 +00:00
Craig Topper
4da632e6e0 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 06:57:25 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00