Commit Graph

581 Commits

Author SHA1 Message Date
Richard Sandiford
d77a7669ec [SystemZ] Handle extensions in RxSBG optimizations
The input to an RxSBG operation can be narrower as long as the upper bits
are don't care.  This fixes a FIXME added in r192783.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 13:35:13 +00:00
Richard Sandiford
d1a4f579bf [SystemZ] Improve handling of SETCC
We previously used the default expansion to SELECT_CC, which in turn would
expand to "LHI; BRC; LHI".  In most cases it's better to use an IPM-based
sequence instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192784 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 11:10:55 +00:00
Rafael Espindola
06957f43f6 Add a MCAsmInfoELF class and factor some code into it.
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 01:34:32 +00:00
Richard Sandiford
f8f993b675 [SystemZ] Use A(G)SI when spilling the target of a constant addition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 08:42:59 +00:00
Will Dietz
e3ba15c794 Add missing #include's to cctype when using isdigit/alpha/etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-12 00:55:57 +00:00
Rafael Espindola
320296a4cf Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 13:08:17 +00:00
Richard Sandiford
e22c56d6d8 [SystemZ] Add comparisons of high words and memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 15:00:44 +00:00
Richard Sandiford
185ef05ad6 [SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:56:23 +00:00
Richard Sandiford
ad366a3f67 [SystemZ] Add immediate addition involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:53:46 +00:00
Richard Sandiford
bd1958d8e9 [SystemZ] Extend test-under-mask support to high GR32s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:41:52 +00:00
Richard Sandiford
f985f01574 [SystemZ] Extend 32-bit RISBG optimizations to high words
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:36:20 +00:00
Richard Sandiford
00f5335ea0 [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
As the comment says, we always want to use STOC for 32-bit stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:33:55 +00:00
Richard Sandiford
5fb8d3144f [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above
Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:31:11 +00:00
Richard Sandiford
b9dcca8265 [SystemZ] Allow integer AND involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:20:41 +00:00
Richard Sandiford
1ff62e182e [SystemZ] Allow integer XOR involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:08:44 +00:00
Richard Sandiford
1c831f7f1f [SystemZ] Allow integer OR involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:22:41 +00:00
Richard Sandiford
645d250b84 [SystemZ] Allow integer insertions with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:18:56 +00:00
Richard Sandiford
4708657097 [SystemZ] Allow selects with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:10:16 +00:00
Richard Sandiford
4c8feae136 [SystemZ] Add patterns to load a constant into a high word (IIHF)
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:02:28 +00:00
Richard Sandiford
79e2ed4d83 [SystemZ] Add register zero extensions involving at least one high word
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:49:07 +00:00
Richard Sandiford
9813dbf396 [SystemZ] Add truncating high-word stores (STCH and STHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:22:49 +00:00
Richard Sandiford
9a05f040e7 [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:19:08 +00:00
Richard Sandiford
ced450f0e6 [SystemZ] Add sign-extending high-word loads (LBH and LHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:11:47 +00:00
Richard Sandiford
55d7d83b6c [SystemZ] Use upper words of GR64s for codegen
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 11:26:28 +00:00
Richard Sandiford
7d0b89bedd [SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 10:31:04 +00:00
Richard Sandiford
16658af535 [SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 12:01:35 +00:00
Richard Sandiford
e09bcad77c [SystemZ] Add definitions of LFH and STFH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 10:50:33 +00:00
Richard Sandiford
eb2f72f454 [SystemZ] Add GRH32 for the high word of a GR64
The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise.  Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended.  The class is needed by
later patches though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 10:45:16 +00:00
Richard Sandiford
745ca1eed7 [SystemZ] Rename subregs and add subreg_h32
Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.

Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.

No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 10:28:35 +00:00
Richard Sandiford
3d307b31b6 [SystemZ] Add change missing from previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 08:54:17 +00:00
Richard Sandiford
514756983e [SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 08:48:38 +00:00
Richard Sandiford
0548a5487a [SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations.  For correctness reasons, it rejects any case
in which the regions might partially overlap.  However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.

This fixes a performance regression seen in bzip2.  We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 15:29:20 +00:00
Richard Sandiford
8dac19c070 [SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible.  That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL).  But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.

Fixes a FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 15:14:04 +00:00
Richard Sandiford
259a6006e8 [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.
Another patch to avoid duplication of encoding information.  Things like
NILF, NILL and NILH are used as both 32-bit and 64-bit instructions.
Here the 64-bit versions are defined as aliases of the 32-bit ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 11:11:53 +00:00
Richard Sandiford
76f8ae87b4 [SystemZ] Define the call instructions as pseudo aliases.
Similar to r191364, but for calls.  This patch also removes the shortening
of BRASL to BRAS within a TU.  Doing that was a bit controversial internally,
since there's a strong expectation with the z assembler that WYWIWYG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:37:17 +00:00
Richard Sandiford
e39a156b92 [SystemZ] Use subregs for 64-bit truncating stores
Another patch to reduce the duplication of encoding information.
Rather than define separate patterns for truncating 64-bit stores,
use the 32-bit stores with a subreg.  No behavioral changed intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:29:47 +00:00
Richard Sandiford
9f3f4bf377 [SystemZ] Define the return instruction as a pseudo alias of BR
This is the first of a few patches to reduce the dupliation of encoding
information.  The return instruction is a normal BR in which one of the
registers is fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:20:08 +00:00
Richard Sandiford
c2b840cb7c [SystemZ] Add instruction-shortening pass
When loading immediates into a GR32, the port prefered LHI, followed by
LLILH or LLILL, followed by IILF.  LHI and IILF are natural 32-bit
operations, but LLILH and LLILL also clear the upper 32 bits of the register.
This was represented as taking a 32-bit subreg of a 64-bit assignment.

Using subregs for something as simple as a move immediate was probably
a bad idea.  Also, I have patches to add support for the high-word facility, 
and we don't want something like LLILH and LLILL to stop the high word of
the same GPR from being used.

This patch therefore uses LHI and IILF to begin with and adds a late
machine-specific pass to use LLILH and LLILL if the other half of the
register is not live.  The high-word patches extend this behavior to
IIHF, LLIHL and LLIHH.

No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:11:07 +00:00
David Majnemer
8ba3f9c900 MC: Remove vestigial PCSymbol field from AsmInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 09:36:11 +00:00
Tim Northover
3e84ad28d4 ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-22 08:21:56 +00:00
Richard Sandiford
e2d6f91d63 [SystemZ] Add unsigned compare-and-branch instructions
For some reason I never got around to adding these at the same time as
the signed versions.  No idea why.

I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether
it should just be replaced with an "is normal" flag.  I'll leave that
for later though.

There are some boundary conditions that can be tweaked, such as preferring
unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256",
but again I'll leave those for a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-18 09:56:40 +00:00
Richard Sandiford
219d2b8695 [SystemZ] Improve extload handling
The port originally had special patterns for extload, mapping them to the
same instructions as sextload.  It seemed neater to have patterns that
match "an extension that is allowed to be signed" and "an extension that
is allowed to be unsigned".

This was originally meant to be a clean-up, but it does improve the handling
of promoted integers a little, as shown by args-06.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 09:03:10 +00:00
Benjamin Kramer
94ee55d4b3 Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 22:04:42 +00:00
Richard Sandiford
7c7b431d2f [SystemZ] Use getTarget{Insert,Extract}Subreg rather than getMachineNode
Just a clean-up, no behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190673 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-13 09:12:44 +00:00
Richard Sandiford
856bf59433 [SystemZ] Try to fold shifts into TMxx
E.g. "SRL %r2, 2; TMLL %r2, 1" => "TMLL %r2, 4".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190672 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-13 09:09:50 +00:00
Joey Gouly
715d98d657 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 10:28:05 +00:00
Richard Sandiford
4c708e586e [SystemZ] Update README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 12:22:45 +00:00
Richard Sandiford
299fdd814f [SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms.  When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit.  The memory forms instead set CC to 1
regardless of the uppermost bit.

Until now, I've tried to make it so that a branch never tests for an
impossible CC value.  E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1.  Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.

I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 10:20:32 +00:00
Bill Wendling
c3cee57f7d Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 02:37:14 +00:00
Richard Sandiford
aff1c6427c [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 11:51:39 +00:00