Chad Rosier
909cb4f2f2
Add support for inlining small memcpys.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce
Fix a performance regression from r144565. Positive offsets were being lowered
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into registers, rather then encoded directly in the load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f
ARM assembly parsing type suffix options for VLDR/VSTR.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:28:39 +00:00
Chad Rosier
57b2997966
Add support for Thumb load/stores with negative offsets.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:22:27 +00:00
Jim Grosbach
430052b084
Tidy up. 80 column.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 17:52:47 +00:00
Chad Rosier
dc9205d9c2
Add support for ARM halfword load/stores and signed byte loads with negative
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offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 04:09:28 +00:00
Chad Rosier
9eb674880b
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2
Add support for emitting both signed- and zero-extend loads. Fix
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SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 02:23:59 +00:00
Daniel Dunbar
b8ebca83f4
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
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- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:10:57 +00:00
Jim Grosbach
9588c10b69
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:58:43 +00:00
Jim Grosbach
742c4bac07
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:31:53 +00:00
Jim Grosbach
4d06138d53
Oops. Missed the isel half of this. revert while I sort that out.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6
ARM assembly parsing for VST1 two-register encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0
ARM optional size suffix for VLDR/VSTR syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:31:03 +00:00
Jim Grosbach
7aef99b677
ARM vldm and vstm VFP instructions can take a data type suffix.
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It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:08:10 +00:00
Jim Grosbach
c3937b97c0
Nuke no longer accurate comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:30:06 +00:00
Andrew Trick
95bc85e4ee
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
Benjamin Kramer
eea66f63d9
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 12:39:41 +00:00
Chad Rosier
1c47de87c7
Rename variables to avoid confusion. No functionallity change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:27:41 +00:00
Chad Rosier
a07d3fc693
Add support for using immediates with select instructions.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 06:20:39 +00:00
Eli Friedman
15f58c56e9
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 03:16:38 +00:00
Chad Rosier
646abbfa30
When loading a value, treat an i1 as an i8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 02:38:59 +00:00
Chad Rosier
4e89d97e3a
Add support for using MVN to materialize negative constants.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:36:21 +00:00
Daniel Dunbar
5ed5506f18
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 00:23:56 +00:00
Jim Grosbach
0352b4679e
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
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rdar://10429490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e
ARM let processInstruction() tranforms chain.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2
Thumb2 parsing for push/pop w/ hi registers in the reglist.
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rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb
Thumb1 diagnostics for reglist on PUSH/POP fix.
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Was not checking the first register in the register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:01:27 +00:00
Jim Grosbach
1b332860ae
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:10:12 +00:00
Chad Rosier
16455ce1a4
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 21:09:49 +00:00
Jim Grosbach
d475f8612b
ARM .thumb_func directive for quoted symbol names.
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Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 20:48:53 +00:00
Jim Grosbach
ee10ff89a2
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 16:44:55 +00:00
Chad Rosier
6cba97c555
For immediate encodings of icmp, zero or sign extend first. Then
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determine if the value is negative and flip the sign accordingly.
rdar://10422026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 01:30:39 +00:00
Daniel Dunbar
affc6cf9d2
llvm-build: Add --native-target and --enable-targets options, and add logic to
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handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 00:50:07 +00:00
Daniel Dunbar
c352caf168
llvm-build: Add an explicit component type to represent targets.
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- Gives us a place to hang target specific metadata (like whether the target has a JIT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 00:49:51 +00:00
Jim Grosbach
c27f6725b9
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 00:02:33 +00:00
Jim Grosbach
3c5d6e4df4
Thumb2 assembly parsing STMDB w/ optional .w suffix.
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rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 23:44:23 +00:00
Eli Friedman
14e809c872
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 23:36:02 +00:00
Chad Rosier
7346347674
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
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rdar://10418009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 21:30:12 +00:00
Chad Rosier
2f2fe417f9
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
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remove a fair number of unnecessary materialized constants.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 03:22:02 +00:00
Evan Cheng
44ee4714a8
Hide cpu name checking in ARMSubtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 01:57:03 +00:00
Evan Cheng
3568a1051e
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08 21:21:09 +00:00
Chad Rosier
66dc8ca04b
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
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No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08 21:12:00 +00:00
Lang Hames
5207bf2177
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
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Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08 18:56:23 +00:00
Pete Cooper
d752e0f7e6
Added invariant field to the DAG.getLoad method and changed all calls.
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When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08 18:42:53 +00:00