Commit Graph

849 Commits

Author SHA1 Message Date
Matt Arsenault
d2f17c4e2b Implement computeKnownBits for min/max nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239378 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-09 00:52:41 +00:00
Fiona Glaser
5a0d6b758c DAGCombiner: don't duplicate (fmul x, c) in visitFNEG if fneg is free
For targets with a free fneg, this fold is always a net loss if it
ends up duplicating the multiply, so definitely avoid it.

This might be true for some targets without a free fneg too, but
I'll leave that for future investigation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 17:52:34 +00:00
Matt Arsenault
35cc03a1ea R600/SI: Reimplement isLegalAddressingMode
Now that we sometimes know the address space, this can
theoretically do a better job.

This needs better test coverage, but this mostly depends on
first updating the loop optimizatiosn to provide the address
space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239053 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 16:17:42 +00:00
Matt Arsenault
e0d4034b76 R600/SI: Fix some cases for load / store of half
Mostly argument loads were producing broken zextloads
from an FP type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239049 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 16:00:27 +00:00
Tom Stellard
8c009e3943 R600: Re-enable sub-reg liveness
The bug in the R600 backend that this uncovered has been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 01:20:04 +00:00
Matt Arsenault
b743320bb3 R600/SI: Fix tests with triples in them
Only set the triple from the command line options.
Some of these were still testing SI features and using the
old r600-- triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238958 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 20:04:05 +00:00
Matthias Braun
fa2b7e5cb4 LiveRangeEdit: Fix liveranges not shrinking on subrange kill.
If a dead instruction we may not only have a last-use in the main live
range but also in a subregister range if subregisters are tracked. We
need to partially rebuild live ranges in both cases.

The testcase only broke when subregister liveness was enabled. I
commited it in the current form because there is currently no flag to
enable/disable subregister liveness.

This fixes PR23720.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 21:26:26 +00:00
Jan Vesely
176d1faf6a R600: Use SIGN_EXTEND_INREG for SEXT loads
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238229 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 18:07:22 +00:00
Tom Stellard
38aad1c16a R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238147 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-25 16:15:54 +00:00
Matt Arsenault
f44ed0919c Add target hook to allow merging stores of nonzero constants
On GPU targets, materializing constants is cheap and stores are
expensive, so only doing this for zero vectors was silly.

Most of the new testcases aren't optimally merged, and are for
later improvements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238108 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-24 00:51:27 +00:00
Tom Stellard
e83e5d460d R600/SI: add pass to mark CF live ranges as non-spillable
Spilling can insert instructions almost anywhere, and this can mess
up control flow lowering in a multitude of ways, due to instruction
reordering. Let's sort this out the easy way: never spill registers
involved with control flow, i.e. saved EXEC masks.

Unfortunately, this does not work at all with optimizations disabled,
as the register allocator ignores spill weights. This should be
addressed in a future commit.

The test was reduced from the "stacks" shader of [1]. Some issues
trigger the machine verifier while another one is checked manually.

[1] http://madebyevan.com/webgl-path-tracing/

v2: only insert pass with optimizations enabled, merge test runs.

Patch by: Grigori Goronzy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 17:13:02 +00:00
Tom Stellard
f36ad4aa04 R600/SI: Remove M0Reg register class
It is no longer used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237142 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 15:00:52 +00:00
Tom Stellard
6ecd744594 R600/SI: Remove explicit m0 operand from DS instructions
Instead add m0 as an implicit operand.  This helps avoid spills
of the m0 register in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237141 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 15:00:49 +00:00
Tom Stellard
9c9f5585b9 R600/SI: Make sendmsg test more strict
We want to make sure that the m0 copies are being cse'd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237134 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 14:18:16 +00:00
Tom Stellard
f17a95a681 R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236307 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-01 03:44:09 +00:00
Tom Stellard
89d0e99f86 R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.

The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.

http://bugs.freedesktop.org/show_bug.cgi?id=90056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236306 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-01 03:44:08 +00:00
Jan Vesely
e3d17d7e9c Reinstate revisions r234755, r234759, r234760
changes:
  Don't apply on hexagon and NVPTX since they no longer claim to support UADDO/USUBO
  Add location to getConstant
  Drop comment about the ops being turned into expand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236240 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-30 17:15:56 +00:00
Tom Stellard
53fec21fbe R600: Fix up for AsmPrinter's OutStreamer being a unique_ptr
Fixes a crash with basically any OpenGL application using the radeonsi
driver.

Patch by: Michel Dänzer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236004 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 17:37:03 +00:00
Matt Arsenault
77420c98f3 R600: Remove / merge redundant testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-26 00:53:33 +00:00
Matt Arsenault
9dd5b1fbd8 R600/SI: Fix verifier error when producing v_madmk_f32
Copy the kill flags when swapping the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 01:57:58 +00:00
Matthias Braun
bd112c28b5 R600/RegisterCoalescer: Enable more rematerialization/add missing testcase
This enables the rematerialization of some R600 MOV instructions in the
RegisterCoalescer and adds a testcase for r235668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 00:25:50 +00:00
Tom Stellard
6d49b023a4 R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235662 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:59:24 +00:00
Tom Stellard
2aab32cade R600/SI: Fix indirect addressing with a negative constant offset
When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235641 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:32:01 +00:00
Matt Arsenault
a37c0d278b R600: Fix always inline pass breaking noinline functions
No test since calls are not actually supported yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235524 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 17:10:44 +00:00
Tom Stellard
4eccd9814f DAGCombine: Remove redundant NaN checks around ISD::FSQRT
This folds:

(select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235333 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 19:38:27 +00:00
Tom Stellard
71fcd2d4d8 R600/SI: Fix verifier error caused by SIAnnotateControlFlow
This pass will always try to insert llvm.SI.ifbreak intrinsics
in the same block that its conditional value is computed in.  This is
a problem when conditions for breaks or continue are computed outside
of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted
outside of the loop.

This patch fixes this problem by inserting the llvm.SI.ifbreak
intrinsics in the loop header when the condition is computed outside
the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-14 14:36:45 +00:00
Jan Vesely
a017ce21ba Revert revisions r234755, r234759, r234760
Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)"
Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO"
Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB"

Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
on hexagon, nvptx, and r600. Revert while I investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234768 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 17:47:15 +00:00
Jan Vesely
4ce8b9c7fb R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO
v2: tighten the sub64 tests
v3: rename to CARRY/BORROW
v4: fixup test cmdline
    add known bits computation
    use sign extend instead of sub 0,x
    better add test
v5: remove redundant break
    move lowering to separate functions
    fix comments

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: arsenm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 16:26:00 +00:00
Jan Vesely
187ac42686 LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB
v2: consider BooleanContents when processing overflow

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: resistor, jholewinsky (nvidia parts)
Differential Revision: http://reviews.llvm.org/D6340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234755 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 15:32:01 +00:00
NAKAMURA Takumi
10a56a29ef llvm/test/CodeGen/R600/fminnum.ll: Relax an expression for NaN on MSVCRT like r204118.
<stdin>:202:2: note: possible intended match here
   2143289344(1.#QNAN0e+00), 2(2.802597e-45)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234719 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 04:54:06 +00:00
Jan Vesely
b7239d3aa5 R600: Make FMIN/MAXNUM legal on all asics
v2: Add tests

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
reviewer: arsenm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234716 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-12 23:45:05 +00:00
Tom Stellard
434e097df8 R600/SI: Don't print offset0/offset1 DS operands when they are 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234379 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-08 01:09:19 +00:00
Ahmed Bougacha
81cd5e82a8 [R600/SI] Fix testcase check line.
Missing colon, instruction typo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233414 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 20:41:42 +00:00
Andrew Trick
9217916725 Complete the MachineScheduler fix made way back in r210390.
"Fix the MachineScheduler's logic for updating ready times for in-order.
 Now the scheduler updates a node's ready time as soon as it is
 scheduled, before releasing dependent nodes."

This fix was only made in one variant of the ScheduleDAGMI driver.
Francois de Ferriere reported the issue in the other bit of code where
it was also needed.
I never got around to coming up with a test case, but it's an
obvious fix that shouldn't be delayed any longer.
I'll try to refactor this code a little better.

I did verify performance on a wide variety of targets and saw no
negative impact with this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-27 06:10:13 +00:00
Marek Olsak
a2705bbd42 R600/SI: Select V_BFE_U32 for and+shift with a non-literal offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233079 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 13:40:34 +00:00
Marek Olsak
226f794fba R600/SI: Custom-select 32-bit S_BFE from bitwise opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233078 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 13:40:27 +00:00
Marek Olsak
945fab3447 R600/SI: Improve BFM support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233077 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 13:40:21 +00:00
Marek Olsak
3f05a5e0ad R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SI
Other f64 opcodes not supported on SI can be lowered in a similar way.

v2: use complex VOP3 patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233076 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 13:40:15 +00:00
Marek Olsak
91c066ae15 R600/SI: Expand fract to floor, then only select V_FRACT on CI
V_FRACT is buggy on SI.

R600-specific code is left intact.

v2: drop the multiclass, use complex VOP3 patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233075 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 13:40:08 +00:00
Matt Arsenault
59a5e979b5 R600/SI: Allow commuting compares
This enables very common cases to switch to the
smaller encoding.

All of the standard LLVM canonicalizations of comparisons
are the opposite of what we want. Compares with constants
are moved to the RHS, but the first operand can be an inline
immediate, literal constant, or SGPR using the 32-bit VOPC
encoding.

There are additional bad canonicalizations that should
also be fixed, such as canonicalizing ge x, k to gt x, (k + 1)
if this makes k no longer an inline immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232988 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:30 +00:00
Tom Stellard
fd58f22744 R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()
This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232957 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 16:06:01 +00:00
Matt Arsenault
2bb644f469 R600: Cleanup test with multiple check prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232901 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-21 19:15:46 +00:00
Tom Stellard
4aee931a46 R600/SI: Add missing CHECK-LABEL lines to a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-20 03:12:42 +00:00
Rafael Espindola
b354ef31cf Teach getDefaultFormat that we only support ELF on some architectures.
This should bring the windows bots back.

It is a bit ugly, but it is better than what we had before: The triple would
say that the object format was COFF, but llc/llvm-mc would produce an ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 22:19:16 +00:00
Rafael Espindola
99739705ac Call EmitFunctionHeader just before EmitFunctionBody.
This avoids switching to .AMDGPU.config and back and hardcoding the
section it switches back to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232479 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 14:34:42 +00:00
Tom Stellard
6ebc34281f R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.

v2: make test more robust

Patch by: Grigori Goronzy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-16 15:53:55 +00:00
David Blaikie
5a70dd1d82 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator
Similar to gep (r230786) and load (r230794) changes.

Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.

(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)

import fileinput
import sys
import re

rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)

def conv(match):
  line = match.group(1)
  line += match.group(4)
  line += ", "
  line += match.group(2)
  return line

line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
  sys.stdout.write(line[off:match.start()])
  sys.stdout.write(conv(match))
  off = match.end()
sys.stdout.write(line[off:])

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 18:20:45 +00:00
Matt Arsenault
462f98dd60 R600/SI: Add test for min / max with immediate
Make sure this isn't getting confused by canonicalizations
of comparisons with a constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 16:43:48 +00:00
Tom Stellard
3d712a6373 R600/SI: Remove _e32 and _e64 suffixes from mnemonics
Instead print them as part of the $dst operand.  The AsmMatcher
requires the 32-bit and 64-bit encodings have the same mnemonic in
order to parse them correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232105 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 21:34:22 +00:00
Marek Olsak
c4ca7b59db R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231659 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 15:48:09 +00:00